2 * Memory Setup stuff - taken from blob memsetup.S
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
7 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
8 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/arch/hardware.h>
32 #include <asm/arch/at91_pmc.h>
33 #include <asm/arch/at91_pio.h>
34 #include <asm/arch/at91_rstc.h>
35 #include <asm/arch/at91_wdt.h>
36 #include <asm/arch/at91sam9_matrix.h>
37 #include <asm/arch/at91sam9_sdramc.h>
38 #include <asm/arch/at91sam9_smc.h>
44 .type lowlevel_init,function
47 mov r5, pc /* r5 = POS1 + 4 current */
49 ldr r0, =POS1 /* r0 = POS1 compile */
51 sub r0, r0, r2 /* r0 = POS1-_TEXT_BASE (POS1 relative) */
52 sub r5, r5, r0 /* r0 = TEXT_BASE-1 */
53 sub r5, r5, #4 /* r1 = text base - current */
55 /* memory control configuration 1 */
72 /* ----------------------------------------------------------------------------
74 * ----------------------------------------------------------------------------
75 * - Check if the PLL is already initialized
76 * ----------------------------------------------------------------------------
78 ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
84 /* ---------------------------------------------------------------------------
85 * - Enable the Main Oscillator
86 * ---------------------------------------------------------------------------
88 ldr r1, =(AT91_BASE_SYS + AT91_CKGR_MOR)
89 ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR)
90 /* Main oscillator Enable register PMC_MOR: */
91 ldr r0, =CONFIG_SYS_MOR_VAL
94 /* Reading the PMC Status to detect when the Main Oscillator is enabled */
95 mov r4, #AT91_PMC_MOSCS
99 cmp r3, #AT91_PMC_MOSCS
102 /* ----------------------------------------------------------------------------
104 * ----------------------------------------------------------------------------
106 * ----------------------------------------------------------------------------
108 ldr r1, =(AT91_BASE_SYS + AT91_CKGR_PLLAR)
109 ldr r0, =CONFIG_SYS_PLLAR_VAL
112 /* Reading the PMC Status register to detect when the PLLA is locked */
113 mov r4, #AT91_PMC_LOCKA
117 cmp r3, #AT91_PMC_LOCKA
120 /* ----------------------------------------------------------------------------
122 * ----------------------------------------------------------------------------
123 * - Switch on the Main Oscillator
124 * ----------------------------------------------------------------------------
126 ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
128 /* -Master Clock Controller register PMC_MCKR */
129 ldr r0, =CONFIG_SYS_MCKR1_VAL
132 /* Reading the PMC Status to detect when the Master clock is ready */
133 mov r4, #AT91_PMC_MCKRDY
137 cmp r3, #AT91_PMC_MCKRDY
140 ldr r0, =CONFIG_SYS_MCKR2_VAL
143 /* Reading the PMC Status to detect when the Master clock is ready */
144 mov r4, #AT91_PMC_MCKRDY
148 cmp r3, #AT91_PMC_MCKRDY
153 /* ----------------------------------------------------------------------------
154 * - memory control configuration 2
155 * ----------------------------------------------------------------------------
157 ldr r0, =(AT91_BASE_SYS + AT91_SDRAMC_TR)
180 /* everything is fine now */
186 .word (AT91_BASE_SYS + AT91_WDT_MR)
187 .word CONFIG_SYS_WDTC_WDMR_VAL
189 /* configure PIOx as EBI0 D[16-31] */
190 #if defined(CONFIG_AT91SAM9263)
191 .word (AT91_BASE_SYS + AT91_PIOD + PIO_PDR)
192 .word CONFIG_SYS_PIOD_PDR_VAL1
193 .word (AT91_BASE_SYS + AT91_PIOD + PIO_PUDR)
194 .word CONFIG_SYS_PIOD_PPUDR_VAL
195 .word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR)
196 .word CONFIG_SYS_PIOD_PPUDR_VAL
197 #elif defined(CONFIG_AT91SAM9261)
198 .word (AT91_BASE_SYS + AT91_PIOC + PIO_PDR)
199 .word CONFIG_SYS_PIOC_PDR_VAL1
200 .word (AT91_BASE_SYS + AT91_PIOC + PIO_PUDR)
201 .word CONFIG_SYS_PIOC_PPUDR_VAL
204 #if defined(AT91_MATRIX_EBI0CSA)
205 .word (AT91_BASE_SYS + AT91_MATRIX_EBI0CSA)
206 .word CONFIG_SYS_MATRIX_EBI0CSA_VAL
207 #else /* AT91_MATRIX_EBICSA */
208 .word (AT91_BASE_SYS + AT91_MATRIX_EBICSA)
209 .word CONFIG_SYS_MATRIX_EBICSA_VAL
213 .word (AT91_BASE_SYS + AT91_SMC_MODE(0))
214 .word CONFIG_SYS_SMC0_MODE0_VAL
216 .word (AT91_BASE_SYS + AT91_SMC_CYCLE(0))
217 .word CONFIG_SYS_SMC0_CYCLE0_VAL
219 .word (AT91_BASE_SYS + AT91_SMC_PULSE(0))
220 .word CONFIG_SYS_SMC0_PULSE0_VAL
222 .word (AT91_BASE_SYS + AT91_SMC_SETUP(0))
223 .word CONFIG_SYS_SMC0_SETUP0_VAL
226 .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
227 .word CONFIG_SYS_SDRC_MR_VAL1
228 .word (AT91_BASE_SYS + AT91_SDRAMC_TR)
229 .word CONFIG_SYS_SDRC_TR_VAL1
230 .word (AT91_BASE_SYS + AT91_SDRAMC_CR)
231 .word CONFIG_SYS_SDRC_CR_VAL
232 .word (AT91_BASE_SYS + AT91_SDRAMC_MDR)
233 .word CONFIG_SYS_SDRC_MDR_VAL
234 .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
235 .word CONFIG_SYS_SDRC_MR_VAL2
236 .word AT91_SDRAM_BASE
237 .word CONFIG_SYS_SDRAM_VAL1
238 .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
239 .word CONFIG_SYS_SDRC_MR_VAL3
240 .word AT91_SDRAM_BASE
241 .word CONFIG_SYS_SDRAM_VAL2
242 .word AT91_SDRAM_BASE
243 .word CONFIG_SYS_SDRAM_VAL3
244 .word AT91_SDRAM_BASE
245 .word CONFIG_SYS_SDRAM_VAL4
246 .word AT91_SDRAM_BASE
247 .word CONFIG_SYS_SDRAM_VAL5
248 .word AT91_SDRAM_BASE
249 .word CONFIG_SYS_SDRAM_VAL6
250 .word AT91_SDRAM_BASE
251 .word CONFIG_SYS_SDRAM_VAL7
252 .word AT91_SDRAM_BASE
253 .word CONFIG_SYS_SDRAM_VAL8
254 .word AT91_SDRAM_BASE
255 .word CONFIG_SYS_SDRAM_VAL9
256 .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
257 .word CONFIG_SYS_SDRC_MR_VAL4
258 .word AT91_SDRAM_BASE
259 .word CONFIG_SYS_SDRAM_VAL10
260 .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
261 .word CONFIG_SYS_SDRC_MR_VAL5
262 .word AT91_SDRAM_BASE
263 .word CONFIG_SYS_SDRAM_VAL11
264 .word (AT91_BASE_SYS + AT91_SDRAMC_TR)
265 .word CONFIG_SYS_SDRC_TR_VAL2
266 .word AT91_SDRAM_BASE
267 .word CONFIG_SYS_SDRAM_VAL12
268 /* User reset enable*/
269 .word (AT91_BASE_SYS + AT91_RSTC_MR)
270 .word CONFIG_SYS_RSTC_RMR_VAL
271 #ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
272 /* MATRIX_MCFG - REMAP all masters */
273 .word (AT91_BASE_SYS + AT91_MATRIX_MCFG0)