2 * armboot - Startup Code for ARM920 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
6 * Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 *************************************************************************
35 * Jump vector table as in table 3.1 in [1]
37 *************************************************************************
43 ldr pc, _undefined_instruction
44 ldr pc, _software_interrupt
45 ldr pc, _prefetch_abort
51 _undefined_instruction: .word undefined_instruction
52 _software_interrupt: .word software_interrupt
53 _prefetch_abort: .word prefetch_abort
54 _data_abort: .word data_abort
55 _not_used: .word not_used
59 .balignl 16,0xdeadbeef
63 *************************************************************************
65 * Startup Code (reset vector)
67 * do important init only if we don't start from memory!
68 * relocate armboot to ram
70 * jump to second stage
72 *************************************************************************
83 * These are defined in the board-specific linker script.
94 /* IRQ stack memory (calculated at run-time) */
95 .globl IRQ_STACK_START
99 /* IRQ stack memory (calculated at run-time) */
100 .globl FIQ_STACK_START
107 * the actual reset code
112 * set the cpu to SVC32 mode
119 /* turn off the watchdog */
120 #if defined(CONFIG_S3C2400)
121 #define pWTCON 0x15300000
122 /* Interupt-Controller base addresses */
123 #define INTMSK 0x14400008
124 /* clock divisor register */
125 #define CLKDIVN 0x14800014
126 #elif defined(CONFIG_S3C2410)
127 #define pWTCON 0x53000000
128 /* Interupt-Controller base addresses */
129 #define INTMSK 0x4A000008
130 #define INTSUBMSK 0x4A00001C
131 /* clock divisor register */
132 #define CLKDIVN 0x4C000014
140 * mask all IRQs by setting all bits in the INTMR - default
145 #if defined(CONFIG_S3C2410)
151 /* FCLK:HCLK:PCLK = 1:2:4 */
152 /* default FCLK is 120 MHz ! */
158 * we do sys-critical inits only at reboot,
159 * not when booting from ram!
161 #ifdef CONFIG_INIT_CRITICAL
165 relocate: /* relocate U-Boot to RAM */
166 adr r0, _start /* r0 <- current position of code */
167 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
168 cmp r0, r1 /* don't reloc during debug */
171 ldr r2, _armboot_start
173 sub r2, r3, r2 /* r2 <- size of armboot */
174 add r2, r0, r2 /* r2 <- source end address */
177 ldmia r0!, {r3-r10} /* copy from source address [r0] */
178 stmia r1!, {r3-r10} /* copy to target address [r1] */
179 cmp r0, r2 /* until source end addreee [r2] */
182 /* Set up the stack */
184 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
185 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
186 sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
187 #ifdef CONFIG_USE_IRQ
188 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
190 sub sp, r0, #12 /* leave 3 words for abort-stack */
193 ldr r0, _bss_start /* find start of bss segment */
194 add r0, r0, #4 /* start at first byte of bss */
195 ldr r1, _bss_end /* stop here */
196 mov r2, #0x00000000 /* clear */
198 clbss_l:str r2, [r0] /* clear loop... */
204 /* try doing this stuff after the relocation */
210 * mask all IRQs by setting all bits in the INTMR - default
216 /* FCLK:HCLK:PCLK = 1:2:4 */
217 /* default FCLK is 120 MHz ! */
221 /* END stuff after relocation */
224 ldr pc, _start_armboot
226 _start_armboot: .word start_armboot
230 *************************************************************************
232 * CPU_init_critical registers
234 * setup important registers
235 * setup memory timing
237 *************************************************************************
243 * flush v4 I/D caches
246 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
247 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
250 * disable MMU stuff and caches
252 mrc p15, 0, r0, c1, c0, 0
253 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
254 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
255 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
256 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
257 mcr p15, 0, r0, c1, c0, 0
261 * before relocating, we have to setup RAM timing
262 * because memory timing is board-dependend, you will
263 * find a memsetup.S in your board directory.
273 *************************************************************************
277 *************************************************************************
283 #define S_FRAME_SIZE 72
305 #define MODE_SVC 0x13
309 * use bad_save_user_regs for abort/prefetch/undef/swi ...
310 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
313 .macro bad_save_user_regs
314 sub sp, sp, #S_FRAME_SIZE
315 stmia sp, {r0 - r12} @ Calling r0-r12
316 ldr r2, _armboot_start
317 sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
318 sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
319 ldmia r2, {r2 - r3} @ get pc, cpsr
320 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
324 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
328 .macro irq_save_user_regs
329 sub sp, sp, #S_FRAME_SIZE
330 stmia sp, {r0 - r12} @ Calling r0-r12
332 stmdb r8, {sp, lr}^ @ Calling SP, LR
333 str lr, [r8, #0] @ Save calling PC
335 str r6, [r8, #4] @ Save CPSR
336 str r0, [r8, #8] @ Save OLD_R0
340 .macro irq_restore_user_regs
341 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
343 ldr lr, [sp, #S_PC] @ Get PC
344 add sp, sp, #S_FRAME_SIZE
345 subs pc, lr, #4 @ return & move spsr_svc into cpsr
349 ldr r13, _armboot_start @ setup our mode stack
350 sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
351 sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
353 str lr, [r13] @ save caller lr / spsr
357 mov r13, #MODE_SVC @ prepare SVC-Mode
364 .macro get_irq_stack @ setup IRQ stack
365 ldr sp, IRQ_STACK_START
368 .macro get_fiq_stack @ setup FIQ stack
369 ldr sp, FIQ_STACK_START
376 undefined_instruction:
379 bl do_undefined_instruction
385 bl do_software_interrupt
405 #ifdef CONFIG_USE_IRQ
412 irq_restore_user_regs
417 /* someone ought to write a more effiction fiq_save_user_regs */
420 irq_restore_user_regs
441 #ifdef CONFIG_S3C2400
442 bl disable_interrupts
448 /* Disable watchdog */
451 /* Initialize watchdog timer count register */
454 /* Enable watchdog timer; assert reset at timer timeout */
463 #else /* ! CONFIG_S3C2400 */
465 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
466 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
467 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
468 bic ip, ip, #0x000f @ ............wcam
469 bic ip, ip, #0x2100 @ ..v....s........
470 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
472 #endif /* CONFIG_S3C2400 */