2 * (C) Copyright 2001-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 /* This code should work for both the S3C2400 and the S3C2410
28 * as they seem to have the same PLL and clock machinery inside.
29 * The different address mapping is handled by the s3c24xx.h files below.
33 #if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
35 #if defined(CONFIG_S3C2400)
37 #elif defined(CONFIG_S3C2410)
44 /* ------------------------------------------------------------------------- */
45 /* NOTE: This describes the proper use of this file.
47 * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
49 * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
50 * the specified bus in HZ.
52 /* ------------------------------------------------------------------------- */
54 static ulong get_PLLCLK(int pllreg)
56 S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
60 r = clk_power->MPLLCON;
61 else if (pllreg == UPLL)
62 r = clk_power->UPLLCON;
66 m = ((r & 0xFF000) >> 12) + 8;
67 p = ((r & 0x003F0) >> 4) + 2;
70 return((CONFIG_SYS_CLK_FREQ * m) / (p << s));
73 /* return FCLK frequency */
76 return(get_PLLCLK(MPLL));
79 /* return HCLK frequency */
82 S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
84 return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
87 /* return PCLK frequency */
90 S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
92 return((clk_power->CLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK());
95 /* return UCLK frequency */
98 return(get_PLLCLK(UPLL));
101 #endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */