3 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* This code should work for both the S3C2400 and the S3C2410
25 * as they seem to have the same I2C controller inside.
26 * The different address mapping is handled by the s3c24xx.h files below.
31 #ifdef CONFIG_DRIVER_S3C24X0_I2C
33 #if defined(CONFIG_S3C2400)
35 #elif defined(CONFIG_S3C2410)
40 #ifdef CONFIG_HARD_I2C
48 #define I2C_NOK_LA 3 /* Lost arbitration */
49 #define I2C_NOK_TOUT 4 /* time out */
51 #define I2CSTAT_BSY 0x20 /* Busy bit */
52 #define I2CSTAT_NACK 0x01 /* Nack bit */
53 #define I2CCON_IRPND 0x10 /* Interrupt pending bit */
54 #define I2C_MODE_MT 0xC0 /* Master Transmit Mode */
55 #define I2C_MODE_MR 0x80 /* Master Receive Mode */
56 #define I2C_START_STOP 0x20 /* START / STOP */
57 #define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
59 #define I2C_TIMEOUT 1 /* 1 second */
62 static int GetI2CSDA(void)
64 S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
67 return (gpio->GPEDAT & 0x8000) >> 15;
70 return (gpio->PGDAT & 0x0020) >> 5;
75 static void SetI2CSDA(int x)
77 rGPEDAT = (rGPEDAT & ~0x8000) | (x&1) << 15;
81 static void SetI2CSCL(int x)
83 S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
86 gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) | (x&1) << 14;
89 gpio->PGDAT = (gpio->PGDAT & ~0x0040) | (x&1) << 6;
94 static int WaitForXfer (void)
96 S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C ();
99 i = I2C_TIMEOUT * 10000;
100 status = i2c->IICCON;
101 while ((i > 0) && !(status & I2CCON_IRPND)) {
103 status = i2c->IICCON;
107 return (status & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
110 static int IsACK (void)
112 S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C ();
114 return (!(i2c->IICSTAT & I2CSTAT_NACK));
117 static void ReadWriteByte (void)
119 S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C ();
121 i2c->IICCON &= ~I2CCON_IRPND;
124 void i2c_init (int speed, int slaveadd)
126 S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C ();
127 S3C24X0_GPIO *const gpio = S3C24X0_GetBase_GPIO ();
128 ulong freq, pres = 16, div;
131 /* wait for some time to give previous transfer a chance to finish */
133 i = I2C_TIMEOUT * 1000;
134 status = i2c->IICSTAT;
135 while ((i > 0) && (status & I2CSTAT_BSY)) {
137 status = i2c->IICSTAT;
141 if ((status & I2CSTAT_BSY) || GetI2CSDA () == 0) {
142 #ifdef CONFIG_S3C2410
143 ulong old_gpecon = gpio->GPECON;
145 #ifdef CONFIG_S3C2400
146 ulong old_gpecon = gpio->PGCON;
148 /* bus still busy probably by (most) previously interrupted transfer */
150 #ifdef CONFIG_S3C2410
151 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
152 gpio->GPECON = (gpio->GPECON & ~0xF0000000) | 0x10000000;
154 #ifdef CONFIG_S3C2400
155 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
156 gpio->PGCON = (gpio->PGCON & ~0x00003c00) | 0x00001000;
159 /* toggle I2CSCL until bus idle */
163 while ((i > 0) && (GetI2CSDA () != 1)) {
173 /* restore pin functions */
174 #ifdef CONFIG_S3C2410
175 gpio->GPECON = old_gpecon;
177 #ifdef CONFIG_S3C2400
178 gpio->PGCON = old_gpecon;
182 /* calculate prescaler and divisor values */
184 if ((freq / pres / (16 + 1)) > speed)
185 /* set prescaler to 512 */
189 while ((freq / pres / (div + 1)) > speed)
192 /* set prescaler, divisor according to freq, also set
194 i2c->IICCON = (div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0);
196 /* init to SLAVE REVEIVE and set slaveaddr */
198 i2c->IICADD = slaveadd;
199 /* program Master Transmit (and implicit STOP) */
200 i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA;
205 * cmd_type is 0 for write, 1 for read.
207 * addr_len can take any value from 0-255, it is only limited
208 * by the char, we could make it larger if needed. If it is
209 * 0 we skip the address write cycle.
212 int i2c_transfer (unsigned char cmd_type,
214 unsigned char addr[],
215 unsigned char addr_len,
216 unsigned char data[], unsigned short data_len)
218 S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C ();
219 int i, status, result;
221 if (data == 0 || data_len == 0) {
222 /*Don't support data transfer of no length or to address 0 */
223 printf ("i2c_transfer: bad call\n");
227 /* Check I2C bus idle */
228 i = I2C_TIMEOUT * 1000;
229 status = i2c->IICSTAT;
230 while ((i > 0) && (status & I2CSTAT_BSY)) {
232 status = i2c->IICSTAT;
236 if (status & I2CSTAT_BSY)
244 if (addr && addr_len) {
247 i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP;
249 while ((i < addr_len) && (result == I2C_OK)) {
250 result = WaitForXfer ();
251 i2c->IICDS = addr[i];
256 while ((i < data_len) && (result == I2C_OK)) {
257 result = WaitForXfer ();
258 i2c->IICDS = data[i];
265 i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP;
267 while ((i < data_len) && (result = I2C_OK)) {
268 result = WaitForXfer ();
269 i2c->IICDS = data[i];
275 if (result == I2C_OK)
276 result = WaitForXfer ();
279 i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA;
284 if (addr && addr_len) {
285 i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA;
288 i2c->IICSTAT |= I2C_START_STOP;
289 result = WaitForXfer ();
292 while ((i < addr_len) && (result == I2C_OK)) {
293 i2c->IICDS = addr[i];
295 result = WaitForXfer ();
301 i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA |
304 result = WaitForXfer ();
306 while ((i < data_len) && (result == I2C_OK)) {
307 /* disable ACK for final READ */
308 if (i == data_len - 1)
309 i2c->IICCON &= ~0x80;
311 result = WaitForXfer ();
312 data[i] = i2c->IICDS;
320 i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA;
323 i2c->IICSTAT |= I2C_START_STOP;
324 result = WaitForXfer ();
328 while ((i < data_len) && (result == I2C_OK)) {
329 /* disable ACK for final READ */
330 if (i == data_len - 1)
331 i2c->IICCON &= ~0x80;
333 result = WaitForXfer ();
334 data[i] = i2c->IICDS;
343 i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA;
348 printf ("i2c_transfer: bad call\n");
356 int i2c_probe (uchar chip)
363 * What is needed is to send the chip address and verify that the
364 * address was <ACK>ed (i.e. there was a chip at that address which
365 * drove the data line low).
367 return (i2c_transfer (I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK);
370 int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
376 printf ("I2C read: addr len %d not supported\n", alen);
381 xaddr[0] = (addr >> 24) & 0xFF;
382 xaddr[1] = (addr >> 16) & 0xFF;
383 xaddr[2] = (addr >> 8) & 0xFF;
384 xaddr[3] = addr & 0xFF;
387 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
389 * EEPROM chips that implement "address overflow" are ones
390 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
391 * address and the extra bits end up in the "chip address"
392 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
393 * four 256 byte chips.
395 * Note that we consider the length of the address field to
396 * still be one byte because the extra address bits are
397 * hidden in the chip address.
400 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
403 i2c_transfer (I2C_READ, chip << 1, &xaddr[4 - alen], alen,
404 buffer, len)) != 0) {
405 printf ("I2c read: failed %d\n", ret);
411 int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
416 printf ("I2C write: addr len %d not supported\n", alen);
421 xaddr[0] = (addr >> 24) & 0xFF;
422 xaddr[1] = (addr >> 16) & 0xFF;
423 xaddr[2] = (addr >> 8) & 0xFF;
424 xaddr[3] = addr & 0xFF;
426 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
428 * EEPROM chips that implement "address overflow" are ones
429 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
430 * address and the extra bits end up in the "chip address"
431 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
432 * four 256 byte chips.
434 * Note that we consider the length of the address field to
435 * still be one byte because the extra address bits are
436 * hidden in the chip address.
439 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
442 (I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer,
445 #endif /* CONFIG_HARD_I2C */
447 #endif /* CONFIG_DRIVER_S3C24X0_I2C */