3 * Lineo, Inc. <www.lineo.com>
4 * Bernhard Kuhn <bkuhn@lineo.com>
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Marius Groeger <mgroeger@sysgo.de>
11 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
12 * Alex Zuepke <azu@sysgo.de>
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 /*#include <asm/io.h>*/
35 #include <asm/arch/hardware.h>
36 /*#include <asm/proc/ptrace.h>*/
38 /* the number of clocks per CONFIG_SYS_HZ */
39 #define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
41 /* macro to read the 16 bit timer */
42 #define READ_TIMER (tmr->TC_CV & 0x0000ffff)
45 static ulong timestamp;
48 void board_reset(void) __attribute__((__weak__));
50 int interrupt_init (void)
54 /* enables TC1.0 clock */
55 *AT91C_PMC_PCER = 1 << AT91C_ID_TC0; /* enable clock */
58 *AT91C_TCB0_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE;
59 tmr->TC_CCR = AT91C_TC_CLKDIS;
60 #define AT91C_TC_CMR_CPCTRG (1 << 14)
61 /* set to MCLK/2 and restart the timer when the vlaue in TC_RC is reached */
62 tmr->TC_CMR = AT91C_TC_TIMER_DIV1_CLOCK | AT91C_TC_CMR_CPCTRG;
65 tmr->TC_RC = TIMER_LOAD_VAL;
67 tmr->TC_CCR = AT91C_TC_SWTRG | AT91C_TC_CLKEN;
74 * timer without interrupts
77 void reset_timer (void)
79 reset_timer_masked ();
82 ulong get_timer (ulong base)
84 return get_timer_masked () - base;
87 void set_timer (ulong t)
92 void udelay (unsigned long usec)
97 void reset_timer_masked (void)
100 lastinc = READ_TIMER;
104 ulong get_timer_raw (void)
106 ulong now = READ_TIMER;
108 if (now >= lastinc) {
110 timestamp += now - lastinc;
112 /* we have an overflow ... */
113 timestamp += now + TIMER_LOAD_VAL - lastinc;
120 ulong get_timer_masked (void)
122 return get_timer_raw()/TIMER_LOAD_VAL;
125 void udelay_masked (unsigned long usec)
131 tmo = CONFIG_SYS_HZ_CLOCK / 1000;
135 endtime = get_timer_raw () + tmo;
138 ulong now = get_timer_raw ();
139 diff = endtime - now;
144 * This function is derived from PowerPC code (read timebase as long long).
145 * On ARM it just returns the timer value.
147 unsigned long long get_ticks(void)
153 * This function is derived from PowerPC code (timebase clock frequency).
154 * On ARM it returns the number of timer ticks per second.
156 ulong get_tbclk (void)
160 tbclk = CONFIG_SYS_HZ;
165 * Reset the cpu by setting up the watchdog timer and let him time out
166 * or toggle a GPIO pin on the AT91RM9200DK board
168 void reset_cpu (ulong ignored)
171 #if defined(CONFIG_AT91RM9200_USART)
172 /*shutdown the console to avoid strange chars during reset */
179 /* this is the way Linux does it */
182 * These defines should be moved into
183 * include/asm-arm/arch-at91rm9200/AT91RM9200.h
184 * as soon as the whitespace fix gets applied.
186 #define AT91C_ST_RSTEN (0x1 << 16)
187 #define AT91C_ST_EXTEN (0x1 << 17)
188 #define AT91C_ST_WDRST (0x1 << 0)
189 #define ST_WDMR *((unsigned long *)0xfffffd08) /* watchdog mode register */
190 #define ST_CR *((unsigned long *)0xfffffd00) /* system clock control register */
192 ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ;
193 ST_CR = AT91C_ST_WDRST;