3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Alex Zuepke <azu@sysgo.de>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/proc-armv/ptrace.h>
32 #include <asm/hardware.h>
35 /* we always count down the max. */
36 #define TIMER_LOAD_VAL 0xffff
37 /* macro to read the 16 bit timer */
38 #define READ_TIMER (IO_TC1D & 0xffff)
42 #define READ_TIMER (0xFFFFFFFF - GET32(T0TC))
46 #define IRQEN (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE))
47 #define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL))
48 #define TM2STAT (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_STATUS))
49 #define TIMER_LOAD_VAL NETARM_GEN_TSTAT_CTC_MASK
50 #define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK)
53 #ifdef CONFIG_S3C4510B
54 /* require interrupts for the S3C4510B */
55 # ifndef CONFIG_USE_IRQ
56 # error CONFIG_USE_IRQ _must_ be defined when using CONFIG_S3C4510B
58 static struct _irq_handler IRQ_HANDLER[N_IRQS];
60 #endif /* CONFIG_S3C4510B */
63 void do_irq (struct pt_regs *pt_regs)
65 #if defined(CONFIG_S3C4510B)
68 while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) { /* sentinal value for no pending interrutps */
69 IRQ_HANDLER[pending>>2].m_func( IRQ_HANDLER[pending>>2].m_data);
71 /* clear pending interrupt */
72 PUT_REG( REG_INTPEND, (1<<(pending>>2)));
74 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
75 /* No do_irq() for IntegratorAP/CM720T as yet */
76 #elif defined(CONFIG_LPC2292)
80 pfnct = (void (*)(void))VICVectAddr;
84 #error do_irq() not defined for this CPU type
89 #ifdef CONFIG_S3C4510B
90 static void default_isr( void *data) {
91 printf ("default_isr(): called for IRQ %d\n", (int)data);
94 static void timer_isr( void *data) {
95 unsigned int *pTime = (unsigned int *)data;
98 if ( !(*pTime % (CONFIG_SYS_HZ/4))) {
100 PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1);
106 #if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
107 /* Use IntegratorAP routines in board/integratorap.c */
110 static ulong timestamp;
111 static ulong lastdec;
113 #if defined(CONFIG_USE_IRQ) && defined(CONFIG_S3C4510B)
114 int arch_interrupt_init (void)
118 /* install default interrupt handlers */
119 for ( i = 0; i < N_IRQS; i++) {
120 IRQ_HANDLER[i].m_data = (void *)i;
121 IRQ_HANDLER[i].m_func = default_isr;
124 /* configure interrupts for IRQ mode */
125 PUT_REG( REG_INTMODE, 0x0);
126 /* clear any pending interrupts */
127 PUT_REG( REG_INTPEND, 0x1FFFFF);
131 /* install interrupt handler for timer */
132 IRQ_HANDLER[INT_TIMER0].m_data = (void *)×tamp;
133 IRQ_HANDLER[INT_TIMER0].m_func = timer_isr;
139 int timer_init (void)
141 #if defined(CONFIG_NETARM)
142 /* disable all interrupts */
145 /* operate timer 2 in non-prescale mode */
146 TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CONFIG_SYS_HZ) |
147 NETARM_GEN_TCTL_ENABLE |
148 NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL));
150 /* set timer 2 counter */
151 lastdec = TIMER_LOAD_VAL;
152 #elif defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
153 /* disable all interrupts */
156 /* operate timer 1 in prescale mode */
157 IO_SYSCON1 |= SYSCON1_TC1M;
159 /* select 2kHz clock source for timer 1 */
160 IO_SYSCON1 &= ~SYSCON1_TC1S;
162 /* set timer 1 counter */
163 lastdec = IO_TC1D = TIMER_LOAD_VAL;
164 #elif defined(CONFIG_S3C4510B)
165 /* configure free running timer 0 */
166 PUT_REG( REG_TMOD, 0x0);
168 CLR_REG( REG_TMOD, TM0_RUN);
170 /* Configure for interval mode */
171 CLR_REG( REG_TMOD, TM1_TOGGLE);
174 * Load Timer data register with count down value.
175 * count_down_val = CONFIG_SYS_SYS_CLK_FREQ/CONFIG_SYS_HZ
177 PUT_REG( REG_TDATA0, (CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ));
180 * Enable global interrupt
181 * Enable timer0 interrupt
183 CLR_REG( REG_INTMASK, ((1<<INT_GLOBAL) | (1<<INT_TIMER0)));
186 SET_REG( REG_TMOD, TM0_RUN);
187 #elif defined(CONFIG_LPC2292)
188 PUT32(T0IR, 0); /* disable all timer0 interrupts */
189 PUT32(T0TCR, 0); /* disable timer0 */
190 PUT32(T0PR, CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ);
193 PUT32(T0TCR, 1); /* enable timer0 */
196 #error No timer_init() defined for this CPU type
203 #endif /* ! IntegratorAP */
206 * timer without interrupts
210 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) || defined(CONFIG_LPC2292)
212 void reset_timer (void)
214 reset_timer_masked ();
217 ulong get_timer (ulong base)
219 return get_timer_masked () - base;
222 void set_timer (ulong t)
227 void udelay (unsigned long usec)
232 tmo *= CONFIG_SYS_HZ;
235 tmo += get_timer (0);
237 while (get_timer_masked () < tmo)
238 #ifdef CONFIG_LPC2292
239 /* GJ - not sure whether this is really needed or a misunderstanding */
240 __asm__ __volatile__(" nop");
246 void reset_timer_masked (void)
249 lastdec = READ_TIMER;
253 ulong get_timer_masked (void)
255 ulong now = READ_TIMER;
257 if (lastdec >= now) {
259 timestamp += lastdec - now;
261 /* we have an overflow ... */
262 timestamp += lastdec + TIMER_LOAD_VAL - now;
269 void udelay_masked (unsigned long usec)
277 tmo *= CONFIG_SYS_HZ;
280 tmo = usec * CONFIG_SYS_HZ;
284 endtime = get_timer_masked () + tmo;
287 ulong now = get_timer_masked ();
288 diff = endtime - now;
292 #elif defined(CONFIG_S3C4510B)
294 ulong get_timer (ulong base)
296 return timestamp - base;
299 void udelay (unsigned long usec)
303 ticks = (usec * CONFIG_SYS_HZ) / 1000000;
305 ticks += get_timer (0);
307 while (get_timer (0) < ticks)
312 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
313 /* No timer routines for IntegratorAP/CM720T as yet */
315 #error Timer routines not defined for this CPU type