2 * (C) Copyright 2001-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * This code should work for both the S3C2400 and the S3C2410
29 * as they seem to have the same PLL and clock machinery inside.
30 * The different address mapping is handled by the s3c24xx.h files below.
40 /* ------------------------------------------------------------------------- */
42 * NOTE: This describes the proper use of this file.
44 * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
46 * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
47 * the specified bus in HZ.
49 /* ------------------------------------------------------------------------- */
51 static ulong get_PLLCLK(int pllreg)
69 m = (r >> 16) & 0x3ff;
73 return m * (CONFIG_SYS_CLK_FREQ / (p * (1 << s)));
76 /* return ARMCORE frequency */
77 ulong get_ARMCLK(void)
83 return get_PLLCLK(APLL) / ((div & 0x7) + 1);
86 /* return FCLK frequency */
89 return get_PLLCLK(APLL);
92 /* return HCLK frequency */
97 uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1;
98 uint hclk_div = ((CLK_DIV0_REG >> 8) & 0x1) + 1;
101 * Bit 7 exists on s3c6410, and not on s3c6400, it is reserved on
102 * s3c6400 and is always 0, and it is indeed running in ASYNC mode
104 if (OTHERS_REG & 0x80)
105 fclk = get_FCLK(); /* SYNC Mode */
107 fclk = get_PLLCLK(MPLL); /* ASYNC Mode */
109 return fclk / (hclk_div * hclkx2_div);
112 /* return PCLK frequency */
116 uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1;
117 uint pre_div = ((CLK_DIV0_REG >> 12) & 0xf) + 1;
119 if (OTHERS_REG & 0x80)
120 fclk = get_FCLK(); /* SYNC Mode */
122 fclk = get_PLLCLK(MPLL); /* ASYNC Mode */
124 return fclk / (hclkx2_div * pre_div);
127 /* return UCLK frequency */
130 return get_PLLCLK(EPLL);
133 int print_cpuinfo(void)
135 printf("\nCPU: S3C6400@%luMHz\n", get_ARMCLK() / 1000000);
136 printf(" Fclk = %luMHz, Hclk = %luMHz, Pclk = %luMHz ",
137 get_FCLK() / 1000000, get_HCLK() / 1000000,
138 get_PCLK() / 1000000);
140 if (OTHERS_REG & 0x80)
141 printf("(SYNC Mode) \n");
143 printf("(ASYNC Mode) \n");