2 * (C) Copyright 2004 Texas Insturments
5 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 * Marius Groeger <mgroeger@sysgo.de>
9 * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
38 static void cache_flush (void);
40 /* read co-processor 15, register #1 (control register) */
41 static unsigned long read_p15_c1 (void)
46 "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
53 /* write to co-processor 15, register #1 (control register) */
54 static void write_p15_c1 (unsigned long value)
57 "mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
65 static void cp_delay (void)
69 /* Many OMAP regs need at least 2 nops */
70 for (i = 0; i < 100; i++)
71 __asm__ __volatile__("nop\n");
74 /* See also ARM Ref. Man. */
75 #define C1_MMU (1 << 0) /* mmu off/on */
76 #define C1_ALIGN (1 << 1) /* alignment faults off/on */
77 #define C1_DC (1 << 2) /* dcache off/on */
78 #define C1_WB (1 << 3) /* merging write buffer on/off */
79 #define C1_BIG_ENDIAN (1 << 7) /* big endian off/on */
80 #define C1_SYS_PROT (1 << 8) /* system protection */
81 #define C1_ROM_PROT (1 << 9) /* ROM protection */
82 #define C1_IC (1 << 12) /* icache off/on */
83 #define C1_HIGH_VECTORS (1 << 13) /* location of vectors: low/high */
84 #define RESERVED_1 (0xf << 3) /* must be 111b for R/W */
91 int cleanup_before_linux (void)
94 * this function is called just before we call linux
95 * it prepares the processor for linux
97 * we turn off caches etc ...
100 disable_interrupts ();
102 /* turn off I/D-cache */
111 /* * reset the cpu by setting up the watchdog timer and let him time out */
112 void reset_cpu (ulong ignored)
114 printf("reset... \n\n\n");
116 /* loop forever and wait for reset to happen */
126 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
128 disable_interrupts ();
134 void icache_enable (void)
138 reg = read_p15_c1 (); /* get control reg. */
140 write_p15_c1 (reg | C1_IC);
143 void icache_disable (void)
147 reg = read_p15_c1 ();
149 write_p15_c1 (reg & ~C1_IC);
152 int icache_status (void)
154 return (read_p15_c1 () & C1_IC) != 0;
157 /* It makes no sense to use the dcache if the MMU is not enabled */
158 void dcache_enable (void)
162 reg = read_p15_c1 ();
164 write_p15_c1 (reg | C1_DC);
167 void dcache_disable (void)
171 reg = read_p15_c1 ();
173 write_p15_c1 (reg & ~C1_DC);
176 int dcache_status (void)
178 return (read_p15_c1 () & C1_DC) != 0;
181 /* flush I/D-cache */
182 static void cache_flush (void)
184 /* invalidate both caches and flush btb */
185 asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (0));
186 /* mem barrier to sync things */
187 asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (0));