2 * armboot - Startup Code for OMP2420/ARM1136 CPU-core
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR)
34 #include <asm/arch/omap2420.h>
38 #ifdef CONFIG_ONENAND_IPL
55 .word 0x12345678 /* now 16*4=64 */
57 ldr pc, _undefined_instruction
58 ldr pc, _software_interrupt
59 ldr pc, _prefetch_abort
65 _undefined_instruction: .word undefined_instruction
66 _software_interrupt: .word software_interrupt
67 _prefetch_abort: .word prefetch_abort
68 _data_abort: .word data_abort
69 _not_used: .word not_used
72 _pad: .word 0x12345678 /* now 16*4=64 */
73 #endif /* CONFIG_ONENAND_IPL */
77 .balignl 16,0xdeadbeef
79 *************************************************************************
81 * Startup Code (reset vector)
83 * do important init only if we don't start from memory!
84 * setup Memory and board specific bits prior to relocation.
85 * relocate armboot to ram
88 *************************************************************************
99 * These are defined in the board-specific linker script.
109 #ifdef CONFIG_USE_IRQ
110 /* IRQ stack memory (calculated at run-time) */
111 .globl IRQ_STACK_START
115 /* IRQ stack memory (calculated at run-time) */
116 .globl FIQ_STACK_START
122 * the actual reset code
127 * set the cpu to SVC32 mode
134 #ifdef CONFIG_OMAP2420H4
135 /* Copy vectors to mask ROM indirect addr */
136 adr r0, _start /* r0 <- current position of code */
137 add r0, r0, #4 /* skip reset vector */
138 mov r2, #64 /* r2 <- size to copy */
139 add r2, r0, r2 /* r2 <- source end address */
140 mov r1, #SRAM_OFFSET0 /* build vect addr */
141 mov r3, #SRAM_OFFSET1
143 mov r3, #SRAM_OFFSET2
146 ldmia r0!, {r3-r10} /* copy from source address [r0] */
147 stmia r1!, {r3-r10} /* copy to target address [r1] */
148 cmp r0, r2 /* until source end address [r2] */
149 bne next /* loop until equal */
150 bl cpy_clk_code /* put dpll adjust code behind vectors */
152 /* the mask ROM code should have PLL and others stable */
153 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
157 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
158 relocate: /* relocate U-Boot to RAM */
159 adr r0, _start /* r0 <- current position of code */
160 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
161 cmp r0, r1 /* don't reloc during debug */
162 #ifndef CONFIG_ONENAND_IPL
164 #endif /* CONFIG_ONENAND_IPL */
166 ldr r2, _armboot_start
168 sub r2, r3, r2 /* r2 <- size of armboot */
169 add r2, r0, r2 /* r2 <- source end address */
172 ldmia r0!, {r3-r10} /* copy from source address [r0] */
173 stmia r1!, {r3-r10} /* copy to target address [r1] */
174 cmp r0, r2 /* until source end addreee [r2] */
176 #endif /* CONFIG_SKIP_RELOCATE_UBOOT */
178 /* Set up the stack */
180 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
181 #ifdef CONFIG_ONENAND_IPL
182 sub sp, r0, #128 /* leave 32 words for abort-stack */
184 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
185 sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
186 #ifdef CONFIG_USE_IRQ
187 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
189 sub sp, r0, #12 /* leave 3 words for abort-stack */
190 #endif /* CONFIG_ONENAND_IPL */
193 ldr r0, _bss_start /* find start of bss segment */
194 ldr r1, _bss_end /* stop here */
195 mov r2, #0x00000000 /* clear */
197 #ifndef CONFIG_ONENAND_IPL
198 clbss_l:str r2, [r0] /* clear loop... */
204 ldr pc, _start_armboot
206 #ifdef CONFIG_ONENAND_IPL
207 _start_armboot: .word start_oneboot
209 _start_armboot: .word start_armboot
214 *************************************************************************
216 * CPU_init_critical registers
218 * setup important registers
219 * setup memory timing
221 *************************************************************************
225 * flush v4 I/D caches
228 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
229 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
232 * disable MMU stuff and caches
234 mrc p15, 0, r0, c1, c0, 0
235 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
236 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
237 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
238 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
239 mcr p15, 0, r0, c1, c0, 0
242 * Jump to board specific initialization... The Mask ROM will have already initialized
243 * basic memory. Go here to bump up clock rate and handle wake up conditions.
245 mov ip, lr /* persevere link reg across call */
246 bl lowlevel_init /* go setup pll,mux,memory */
247 mov lr, ip /* restore link */
248 mov pc, lr /* back to my caller */
250 #ifndef CONFIG_ONENAND_IPL
252 *************************************************************************
256 *************************************************************************
261 #define S_FRAME_SIZE 72
283 #define MODE_SVC 0x13
287 * use bad_save_user_regs for abort/prefetch/undef/swi ...
288 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
291 .macro bad_save_user_regs
292 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
293 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
295 ldr r2, _armboot_start
296 sub r2, r2, #(CFG_MALLOC_LEN)
297 sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
298 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
299 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
303 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
304 mov r0, sp @ save current stack into r0 (param register)
307 .macro irq_save_user_regs
308 sub sp, sp, #S_FRAME_SIZE
309 stmia sp, {r0 - r12} @ Calling r0-r12
310 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
311 stmdb r8, {sp, lr}^ @ Calling SP, LR
312 str lr, [r8, #0] @ Save calling PC
314 str r6, [r8, #4] @ Save CPSR
315 str r0, [r8, #8] @ Save OLD_R0
319 .macro irq_restore_user_regs
320 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
322 ldr lr, [sp, #S_PC] @ Get PC
323 add sp, sp, #S_FRAME_SIZE
324 subs pc, lr, #4 @ return & move spsr_svc into cpsr
328 ldr r13, _armboot_start @ setup our mode stack (enter in banked mode)
329 sub r13, r13, #(CFG_MALLOC_LEN) @ move past malloc pool
330 sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack
332 str lr, [r13] @ save caller lr in position 0 of saved stack
333 mrs lr, spsr @ get the spsr
334 str lr, [r13, #4] @ save spsr in position 1 of saved stack
336 mov r13, #MODE_SVC @ prepare SVC-Mode
338 msr spsr, r13 @ switch modes, make sure moves will execute
339 mov lr, pc @ capture return pc
340 movs pc, lr @ jump to next instruction & switch modes.
343 .macro get_bad_stack_swi
344 sub r13, r13, #4 @ space on current stack for scratch reg.
345 str r0, [r13] @ save R0's value.
346 ldr r0, _armboot_start @ get data regions start
347 sub r0, r0, #(CFG_MALLOC_LEN) @ move past malloc pool
348 sub r0, r0, #(CFG_GBL_DATA_SIZE+8) @ move past gbl and a couple spots for abort stack
349 str lr, [r0] @ save caller lr in position 0 of saved stack
350 mrs r0, spsr @ get the spsr
351 str lr, [r0, #4] @ save spsr in position 1 of saved stack
352 ldr r0, [r13] @ restore r0
353 add r13, r13, #4 @ pop stack entry
356 .macro get_irq_stack @ setup IRQ stack
357 ldr sp, IRQ_STACK_START
360 .macro get_fiq_stack @ setup FIQ stack
361 ldr sp, FIQ_STACK_START
363 #endif /* CONFIG_ONENAND_IPL */
368 #ifdef CONFIG_ONENAND_IPL
371 ldr sp, _TEXT_BASE /* use 32 words about stack */
372 bl hang /* hang and never return */
373 #else /* !CONFIG_ONENAND IPL */
375 undefined_instruction:
378 bl do_undefined_instruction
384 bl do_software_interrupt
404 #ifdef CONFIG_USE_IRQ
411 irq_restore_user_regs
416 /* someone ought to write a more effiction fiq_save_user_regs */
419 irq_restore_user_regs
437 .global arm1136_cache_flush
439 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
440 mov pc, lr @ back to caller
442 #if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR)
443 /* Use the IntegratorCP function from board/integratorcp/platform.S */
449 ldr r1, rstctl /* get addr for global reset reg */
450 mov r3, #0x2 /* full reset pll+mpu */
451 str r3, [r1] /* force reset */
456 .word PM_RSTCTRL_WKUP
459 #endif /* CONFIG_ONENAND_IPL */