2 * armboot - Startup Code for OMP2420/ARM1136 CPU-core
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/arch/omap2420.h>
37 ldr pc, _undefined_instruction
38 ldr pc, _software_interrupt
39 ldr pc, _prefetch_abort
45 _undefined_instruction: .word undefined_instruction
46 _software_interrupt: .word software_interrupt
47 _prefetch_abort: .word prefetch_abort
48 _data_abort: .word data_abort
49 _not_used: .word not_used
52 _pad: .word 0x12345678 /* now 16*4=64 */
56 .balignl 16,0xdeadbeef
58 *************************************************************************
60 * Startup Code (reset vector)
62 * do important init only if we don't start from memory!
63 * setup Memory and board specific bits prior to relocation.
64 * relocate armboot to ram
67 *************************************************************************
78 * These are defined in the board-specific linker script.
89 /* IRQ stack memory (calculated at run-time) */
90 .globl IRQ_STACK_START
94 /* IRQ stack memory (calculated at run-time) */
95 .globl FIQ_STACK_START
101 * the actual reset code
106 * set the cpu to SVC32 mode
113 #ifdef CONFIG_OMAP2420H4
114 /* Copy vectors to mask ROM indirect addr */
115 adr r0, _start /* r0 <- current position of code */
116 add r0, r0, #4 /* skip reset vector */
117 mov r2, #64 /* r2 <- size to copy */
118 add r2, r0, r2 /* r2 <- source end address */
119 mov r1, #SRAM_OFFSET0 /* build vect addr */
120 mov r3, #SRAM_OFFSET1
122 mov r3, #SRAM_OFFSET2
125 ldmia r0!, {r3-r10} /* copy from source address [r0] */
126 stmia r1!, {r3-r10} /* copy to target address [r1] */
127 cmp r0, r2 /* until source end address [r2] */
128 bne next /* loop until equal */
129 bl cpy_clk_code /* put dpll adjust code behind vectors */
131 /* the mask ROM code should have PLL and others stable */
134 relocate: /* relocate U-Boot to RAM */
135 adr r0, _start /* r0 <- current position of code */
136 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
137 cmp r0, r1 /* don't reloc during debug */
140 ldr r2, _armboot_start
142 sub r2, r3, r2 /* r2 <- size of armboot */
143 add r2, r0, r2 /* r2 <- source end address */
146 ldmia r0!, {r3-r10} /* copy from source address [r0] */
147 stmia r1!, {r3-r10} /* copy to target address [r1] */
148 cmp r0, r2 /* until source end addreee [r2] */
151 /* Set up the stack */
153 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
154 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
155 sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
156 #ifdef CONFIG_USE_IRQ
157 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
159 sub sp, r0, #12 /* leave 3 words for abort-stack */
162 ldr r0, _bss_start /* find start of bss segment */
163 ldr r1, _bss_end /* stop here */
164 mov r2, #0x00000000 /* clear */
166 clbss_l:str r2, [r0] /* clear loop... */
171 ldr pc, _start_armboot
173 _start_armboot: .word start_armboot
177 *************************************************************************
179 * CPU_init_critical registers
181 * setup important registers
182 * setup memory timing
184 *************************************************************************
188 * flush v4 I/D caches
191 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
192 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
195 * disable MMU stuff and caches
197 mrc p15, 0, r0, c1, c0, 0
198 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
199 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
200 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
201 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
202 mcr p15, 0, r0, c1, c0, 0
205 * Jump to board specific initialization... The Mask ROM will have already initialized
206 * basic memory. Go here to bump up clock rate and handle wake up conditions.
208 mov ip, lr /* persevere link reg across call */
209 bl platformsetup /* go setup pll,mux,memory */
210 mov lr, ip /* restore link */
211 mov pc, lr /* back to my caller */
213 *************************************************************************
217 *************************************************************************
222 #define S_FRAME_SIZE 72
244 #define MODE_SVC 0x13
248 * use bad_save_user_regs for abort/prefetch/undef/swi ...
249 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
252 .macro bad_save_user_regs
253 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
254 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
256 ldr r2, _armboot_start
257 sub r2, r2, #(CFG_MALLOC_LEN)
258 sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
259 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
260 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
264 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
265 mov r0, sp @ save current stack into r0 (param register)
268 .macro irq_save_user_regs
269 sub sp, sp, #S_FRAME_SIZE
270 stmia sp, {r0 - r12} @ Calling r0-r12
271 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
272 stmdb r8, {sp, lr}^ @ Calling SP, LR
273 str lr, [r8, #0] @ Save calling PC
275 str r6, [r8, #4] @ Save CPSR
276 str r0, [r8, #8] @ Save OLD_R0
280 .macro irq_restore_user_regs
281 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
283 ldr lr, [sp, #S_PC] @ Get PC
284 add sp, sp, #S_FRAME_SIZE
285 subs pc, lr, #4 @ return & move spsr_svc into cpsr
289 ldr r13, _armboot_start @ setup our mode stack (enter in banked mode)
290 sub r13, r13, #(CFG_MALLOC_LEN) @ move past malloc pool
291 sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack
293 str lr, [r13] @ save caller lr in position 0 of saved stack
294 mrs lr, spsr @ get the spsr
295 str lr, [r13, #4] @ save spsr in position 1 of saved stack
297 mov r13, #MODE_SVC @ prepare SVC-Mode
299 msr spsr, r13 @ switch modes, make sure moves will execute
300 mov lr, pc @ capture return pc
301 movs pc, lr @ jump to next instruction & switch modes.
304 .macro get_bad_stack_swi
305 sub r13, r13, #4 @ space on current stack for scratch reg.
306 str r0, [r13] @ save R0's value.
307 ldr r0, _armboot_start @ get data regions start
308 sub r0, r0, #(CFG_MALLOC_LEN) @ move past malloc pool
309 sub r0, r0, #(CFG_GBL_DATA_SIZE+8) @ move past gbl and a couple spots for abort stack
310 str lr, [r0] @ save caller lr in position 0 of saved stack
311 mrs r0, spsr @ get the spsr
312 str lr, [r0, #4] @ save spsr in position 1 of saved stack
313 ldr r0, [r13] @ restore r0
314 add r13, r13, #4 @ pop stack entry
317 .macro get_irq_stack @ setup IRQ stack
318 ldr sp, IRQ_STACK_START
321 .macro get_fiq_stack @ setup FIQ stack
322 ldr sp, FIQ_STACK_START
329 undefined_instruction:
332 bl do_undefined_instruction
338 bl do_software_interrupt
358 #ifdef CONFIG_USE_IRQ
365 irq_restore_user_regs
370 /* someone ought to write a more effiction fiq_save_user_regs */
373 irq_restore_user_regs
391 .global arm1136_cache_flush
393 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
394 mov pc, lr @ back to caller
399 ldr r1, rstctl /* get addr for global reset reg */
400 mov r3, #0x2 /* full reset pll+mpu */
401 str r3, [r1] /* force reset */
406 .word PM_RSTCTRL_WKUP