2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2001 Josh Huber <huber@mclx.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 /* U-Boot - Startup Code for PowerPC based Embedded Boards
29 * The processor starts at 0xfff00100 and the code is executed
30 * from flash. The code is organized to be at an other address
31 * in memory, but as long we don't jump around before relocating.
32 * board_init lies at a quite high address and when the cpu has
33 * jumped there, everything is ok.
39 #include <ppc_asm.tmpl>
42 #include <asm/cache.h>
45 #include <galileo/gt64260R.h>
47 #ifndef CONFIG_IDENT_STRING
48 #define CONFIG_IDENT_STRING ""
51 /* We don't want the MMU yet.
54 /* Machine Check and Recoverable Interr. */
55 #define MSR_KERNEL ( MSR_ME | MSR_RI )
58 * Set up GOT: Global Offset Table
60 * Use r14 to access the GOT
63 GOT_ENTRY(_GOT2_TABLE_)
64 GOT_ENTRY(_FIXUP_TABLE_)
67 GOT_ENTRY(_start_of_vectors)
68 GOT_ENTRY(_end_of_vectors)
69 GOT_ENTRY(transfer_to_handler)
72 GOT_ENTRY(__bss_start)
76 * r3 - 1st arg to board_init(): IMMP pointer
77 * r4 - 2nd arg to board_init(): boot flag
80 .long 0x27051956 /* U-Boot Magic Number */
84 .ascii " (", __DATE__, " - ", __TIME__, ")"
85 .ascii CONFIG_IDENT_STRING, "\0"
90 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
94 . = EXC_OFF_SYS_RESET + 0x10
98 li r21, BOOTFLAG_WARM /* Software reboot */
102 /* the boot code is located below the exception table */
104 .globl _start_of_vectors
108 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
110 /* Data Storage exception. "Never" generated on the 860. */
111 STD_EXCEPTION(0x300, DataStorage, UnknownException)
113 /* Instruction Storage exception. "Never" generated on the 860. */
114 STD_EXCEPTION(0x400, InstStorage, UnknownException)
116 /* External Interrupt exception. */
117 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
119 /* Alignment exception. */
127 addi r3,r1,STACK_FRAME_OVERHEAD
129 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
130 lwz r6,GOT(transfer_to_handler)
134 .long AlignmentException - _start + EXC_OFF_SYS_RESET
135 .long int_return - _start + EXC_OFF_SYS_RESET
137 /* Program check exception */
141 addi r3,r1,STACK_FRAME_OVERHEAD
143 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
144 lwz r6,GOT(transfer_to_handler)
148 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
149 .long int_return - _start + EXC_OFF_SYS_RESET
151 /* No FPU on MPC8xx. This exception is not supposed to happen.
153 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
155 /* I guess we could implement decrementer, and may have
156 * to someday for timekeeping.
158 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
159 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
160 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
164 * r0 - SYSCALL number
168 addis r11,r0,0 /* get functions table addr */
169 ori r11,r11,0 /* Note: this code is patched in trap_init */
170 addis r12,r0,0 /* get number of functions */
176 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
180 li r20,0xd00-4 /* Get stack pointer */
182 subi r12,r12,12 /* Adjust stack pointer */
183 li r0,0xc00+_end_back-SystemCall
184 cmplw 0, r0, r12 /* Check stack overflow */
195 li r12,0xc00+_back-SystemCall
204 mfmsr r11 /* Disable interrupts */
208 SYNC /* Some chip revs need this... */
212 li r12,0xd00-4 /* restore regs */
222 addi r12,r12,12 /* Adjust stack pointer */
230 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
232 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
233 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
236 * On the MPC8xx, this is a software emulation interrupt. It
237 * occurs for all unimplemented and illegal instructions.
239 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
241 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
242 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
243 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
244 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
246 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
247 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
248 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
249 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
250 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
251 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
252 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
254 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
255 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
256 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
257 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
259 .globl _end_of_vectors
266 /* disable everything */
275 /* init the L2 cache */
276 addis r3, r0, L2_INIT@h
277 ori r3, r3, L2_INIT@l
281 #if defined(CONFIG_ALTIVEC) && defined(CONFIG_74xx)
284 * dssall instruction, gas doesn't have it yet
285 * ...for altivec, data stream stop all this probably
286 * isn't needed unless we warm (software) reboot U-Boot
291 /* invalidate the L2 cache */
292 bl l2cache_invalidate
295 #ifdef CFG_BOARD_ASM_INIT
301 * Calculate absolute address in FLASH and jump there
302 *------------------------------------------------------*/
303 lis r3, CFG_MONITOR_BASE@h
304 ori r3, r3, CFG_MONITOR_BASE@l
305 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
310 /* let the C-code set up the rest */
312 /* Be careful to keep code relocatable ! */
313 /*------------------------------------------------------*/
315 /* perform low-level init */
316 /* sdram init, galileo init, etc */
317 /* r3: NHR bit from HID0 */
324 * Cache must be enabled here for stack-in-cache trick.
325 * This means we need to enable the BATS.
327 * 1) for the EVB, original gt regs need to be mapped
328 * 2) need to have an IBAT for the 0xf region,
329 * we are running there!
330 * Cache should be turned on after BATs, since by default
331 * everything is write-through.
332 * The init-mem BAT can be reused after reloc. The old
333 * gt-regs BAT can be reused after board_init_f calls
334 * board_pre_init (EVB only).
336 #if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC)
337 /* enable address translation */
341 /* enable and invalidate the data cache */
345 #ifdef CFG_INIT_RAM_LOCK
350 /* set up the stack pointer in our newly created
352 lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
353 ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
355 li r0, 0 /* Make room for stack frame header and */
356 stwu r0, -4(r1) /* clear final stack frame so that */
357 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
359 GET_GOT /* initialize GOT access */
361 /* run low-level CPU init code (from Flash) */
368 /* run 1st part of board init code (from Flash) */
374 .globl invalidate_bats
376 /* invalidate BATs */
390 /* setup_bats - set them up to some initial state */
396 addis r4, r0, CFG_IBAT0L@h
397 ori r4, r4, CFG_IBAT0L@l
398 addis r3, r0, CFG_IBAT0U@h
399 ori r3, r3, CFG_IBAT0U@l
405 addis r4, r0, CFG_DBAT0L@h
406 ori r4, r4, CFG_DBAT0L@l
407 addis r3, r0, CFG_DBAT0U@h
408 ori r3, r3, CFG_DBAT0U@l
414 addis r4, r0, CFG_IBAT1L@h
415 ori r4, r4, CFG_IBAT1L@l
416 addis r3, r0, CFG_IBAT1U@h
417 ori r3, r3, CFG_IBAT1U@l
423 addis r4, r0, CFG_DBAT1L@h
424 ori r4, r4, CFG_DBAT1L@l
425 addis r3, r0, CFG_DBAT1U@h
426 ori r3, r3, CFG_DBAT1U@l
432 addis r4, r0, CFG_IBAT2L@h
433 ori r4, r4, CFG_IBAT2L@l
434 addis r3, r0, CFG_IBAT2U@h
435 ori r3, r3, CFG_IBAT2U@l
441 addis r4, r0, CFG_DBAT2L@h
442 ori r4, r4, CFG_DBAT2L@l
443 addis r3, r0, CFG_DBAT2U@h
444 ori r3, r3, CFG_DBAT2U@l
450 addis r4, r0, CFG_IBAT3L@h
451 ori r4, r4, CFG_IBAT3L@l
452 addis r3, r0, CFG_IBAT3U@h
453 ori r3, r3, CFG_IBAT3U@l
459 addis r4, r0, CFG_DBAT3L@h
460 ori r4, r4, CFG_DBAT3L@l
461 addis r3, r0, CFG_DBAT3U@h
462 ori r3, r3, CFG_DBAT3U@l
467 /* bats are done, now invalidate the TLBs */
470 addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */
483 .globl enable_addr_trans
485 /* enable address translation */
487 ori r5, r5, (MSR_IR | MSR_DR)
492 .globl disable_addr_trans
494 /* disable address translation */
497 andi. r0, r3, (MSR_IR | MSR_DR)
505 * This code finishes saving the registers to the exception frame
506 * and jumps to the appropriate handler for the exception.
507 * Register r21 is pointer into trap frame, r1 has new stack pointer.
509 .globl transfer_to_handler
520 andi. r24,r23,0x3f00 /* get vector offset */
524 mtspr SPRG2,r22 /* r1 is now kernel sp */
525 lwz r24,0(r23) /* virtual address of handler */
526 lwz r23,4(r23) /* where to go when done */
531 rfi /* jump to handler, enable MMU */
534 mfmsr r28 /* Disable interrupts */
538 SYNC /* Some chip revs need this... */
553 lwz r2,_NIP(r1) /* Restore environment */
572 /*-----------------------------------------------------------------------*/
574 * void relocate_code (addr_sp, gd, addr_moni)
576 * This "function" does not return, instead it continues in RAM
577 * after relocating the monitor code.
581 * r5 = length in bytes
586 mr r1, r3 /* Set new stack pointer */
587 mr r9, r4 /* Save copy of Global Data pointer */
588 mr r10, r5 /* Save copy of Destination Address */
590 mr r3, r5 /* Destination Address */
591 lis r4, CFG_MONITOR_BASE@h /* Source Address */
592 ori r4, r4, CFG_MONITOR_BASE@l
593 lis r5, CFG_MONITOR_LEN@h /* Length in Bytes */
594 ori r5, r5, CFG_MONITOR_LEN@l
595 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
600 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
606 /* First our own GOT */
608 /* then the one used by the C code */
615 bl board_relocate_rom
617 mr r3, r10 /* Destination Address */
618 lis r4, CFG_MONITOR_BASE@h /* Source Address */
619 ori r4, r4, CFG_MONITOR_BASE@l
620 lis r5, CFG_MONITOR_LEN@h /* Length in Bytes */
621 ori r5, r5, CFG_MONITOR_LEN@l
622 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
627 beq cr1,4f /* In place copy is not necessary */
628 beq 7f /* Protect against 0 count */
647 * Now flush the cache: note that we must start from a cache aligned
648 * address. Otherwise we might miss one cache line.
652 beq 7f /* Always flush prefetch queue in any case */
660 sync /* Wait for all dcbst to complete on bus */
666 7: sync /* Wait for all icbi to complete on bus */
670 * We are done. Do not return, instead branch to second part of board
671 * initialization, now running from RAM.
673 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
682 * Relocation Function, r14 point to got2+0x8000
684 * Adjust got2 pointers, no need to check for 0, this code
685 * already puts a few entries in the table.
687 li r0,__got2_entries@sectoff@l
688 la r3,GOT(_GOT2_TABLE_)
689 lwz r11,GOT(_GOT2_TABLE_)
699 * Now adjust the fixups and the pointers to the fixups
700 * in case we need to move ourselves again.
702 2: li r0,__fixup_entries@sectoff@l
703 lwz r3,GOT(_FIXUP_TABLE_)
717 * Now clear BSS segment
719 lwz r3,GOT(__bss_start)
732 mr r3, r10 /* Destination Address */
733 #ifdef CONFIG_AMIGAONEG3SE
734 mr r4, r9 /* Use RAM copy of the global data */
738 /* not reached - end relocate_code */
739 /*-----------------------------------------------------------------------*/
741 /* Problems accessing "end" in C, so do it here */
748 * Copy exception vector code to low memory
751 * r7: source address, r8: end address, r9: target address
756 lwz r8, GOT(_end_of_vectors)
758 rlwinm r9, r7, 0, 18, 31 /* _start & 0x3FFF */
761 bgelr /* return if r7>=r8 - just in case */
763 mflr r4 /* save link register */
773 * relocate `hdlr' and `int_return' entries
775 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
776 li r8, Alignment - _start + EXC_OFF_SYS_RESET
779 addi r7, r7, 0x100 /* next exception vector */
783 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
786 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
789 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
790 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
793 addi r7, r7, 0x100 /* next exception vector */
797 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
798 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
801 addi r7, r7, 0x100 /* next exception vector */
805 /* enable execptions from RAM vectors */
811 mtlr r4 /* restore link register */
815 * Function: relocate entries for one exception vector
818 lwz r0, 0(r7) /* hdlr ... */
819 add r0, r0, r3 /* ... += dest_addr */
822 lwz r0, 4(r7) /* int_return ... */
823 add r0, r0, r3 /* ... += dest_addr */
831 #ifdef CFG_INIT_RAM_LOCK
833 /* Allocate Initial RAM in data cache.
835 lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
836 ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
837 li r2, ((CFG_INIT_RAM_END & ~31) + \
838 (CFG_INIT_RAM_ADDR & 31) + 31) / 32
845 /* Lock the data cache */
853 .globl unlock_ram_in_cache
855 /* invalidate the INIT_RAM section */
856 lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
857 ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
858 li r2, ((CFG_INIT_RAM_END & ~31) + \
859 (CFG_INIT_RAM_ADDR & 31) + 31) / 32
864 sync /* Wait for all icbi to complete on bus */
867 /* Unlock the data cache and invalidate it */