2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2001 Josh Huber <huber@mclx.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 /* U-Boot - Startup Code for PowerPC based Embedded Boards
29 * The processor starts at 0xfff00100 and the code is executed
30 * from flash. The code is organized to be at an other address
31 * in memory, but as long we don't jump around before relocating.
32 * board_init lies at a quite high address and when the cpu has
33 * jumped there, everything is ok.
39 #include <ppc_asm.tmpl>
42 #include <asm/cache.h>
45 #include <galileo/gt64260R.h>
47 #ifndef CONFIG_IDENT_STRING
48 #define CONFIG_IDENT_STRING ""
51 /* We don't want the MMU yet.
54 /* Machine Check and Recoverable Interr. */
55 #define MSR_KERNEL ( MSR_ME | MSR_RI )
58 * Set up GOT: Global Offset Table
60 * Use r14 to access the GOT
63 GOT_ENTRY(_GOT2_TABLE_)
64 GOT_ENTRY(_FIXUP_TABLE_)
67 GOT_ENTRY(_start_of_vectors)
68 GOT_ENTRY(_end_of_vectors)
69 GOT_ENTRY(transfer_to_handler)
73 GOT_ENTRY(__bss_start)
77 * r3 - 1st arg to board_init(): IMMP pointer
78 * r4 - 2nd arg to board_init(): boot flag
81 .long 0x27051956 /* U-Boot Magic Number */
85 .ascii " (", __DATE__, " - ", __TIME__, ")"
86 .ascii CONFIG_IDENT_STRING, "\0"
91 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
95 . = EXC_OFF_SYS_RESET + 0x10
99 li r21, BOOTFLAG_WARM /* Software reboot */
103 /* the boot code is located below the exception table */
105 .globl _start_of_vectors
109 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
111 /* Data Storage exception. "Never" generated on the 860. */
112 STD_EXCEPTION(0x300, DataStorage, UnknownException)
114 /* Instruction Storage exception. "Never" generated on the 860. */
115 STD_EXCEPTION(0x400, InstStorage, UnknownException)
117 /* External Interrupt exception. */
118 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
120 /* Alignment exception. */
128 addi r3,r1,STACK_FRAME_OVERHEAD
130 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
131 lwz r6,GOT(transfer_to_handler)
135 .long AlignmentException - _start + EXC_OFF_SYS_RESET
136 .long int_return - _start + EXC_OFF_SYS_RESET
138 /* Program check exception */
142 addi r3,r1,STACK_FRAME_OVERHEAD
144 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
145 lwz r6,GOT(transfer_to_handler)
149 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
150 .long int_return - _start + EXC_OFF_SYS_RESET
152 /* No FPU on MPC8xx. This exception is not supposed to happen.
154 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
156 /* I guess we could implement decrementer, and may have
157 * to someday for timekeeping.
159 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
160 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
161 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
165 * r0 - SYSCALL number
169 addis r11,r0,0 /* get functions table addr */
170 ori r11,r11,0 /* Note: this code is patched in trap_init */
171 addis r12,r0,0 /* get number of functions */
177 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
181 li r20,0xd00-4 /* Get stack pointer */
183 subi r12,r12,12 /* Adjust stack pointer */
184 li r0,0xc00+_end_back-SystemCall
185 cmplw 0, r0, r12 /* Check stack overflow */
196 li r12,0xc00+_back-SystemCall
205 mfmsr r11 /* Disable interrupts */
209 SYNC /* Some chip revs need this... */
213 li r12,0xd00-4 /* restore regs */
223 addi r12,r12,12 /* Adjust stack pointer */
231 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
233 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
234 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
237 * On the MPC8xx, this is a software emulation interrupt. It
238 * occurs for all unimplemented and illegal instructions.
240 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
242 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
243 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
244 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
245 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
247 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
248 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
249 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
250 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
251 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
252 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
253 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
255 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
256 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
257 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
258 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
260 .globl _end_of_vectors
267 /* disable everything */
276 /* init the L2 cache */
277 addis r3, r0, L2_INIT@h
278 ori r3, r3, L2_INIT@l
282 #if defined(CONFIG_ALTIVEC) && defined(CONFIG_74xx)
285 * dssall instruction, gas doesn't have it yet
286 * ...for altivec, data stream stop all this probably
287 * isn't needed unless we warm (software) reboot U-Boot
292 /* invalidate the L2 cache */
293 bl l2cache_invalidate
296 #ifdef CFG_BOARD_ASM_INIT
302 * Calculate absolute address in FLASH and jump there
303 *------------------------------------------------------*/
304 lis r3, CFG_MONITOR_BASE@h
305 ori r3, r3, CFG_MONITOR_BASE@l
306 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
311 /* let the C-code set up the rest */
313 /* Be careful to keep code relocatable ! */
314 /*------------------------------------------------------*/
316 /* perform low-level init */
317 /* sdram init, galileo init, etc */
318 /* r3: NHR bit from HID0 */
325 * Cache must be enabled here for stack-in-cache trick.
326 * This means we need to enable the BATS.
328 * 1) for the EVB, original gt regs need to be mapped
329 * 2) need to have an IBAT for the 0xf region,
330 * we are running there!
331 * Cache should be turned on after BATs, since by default
332 * everything is write-through.
333 * The init-mem BAT can be reused after reloc. The old
334 * gt-regs BAT can be reused after board_init_f calls
335 * board_pre_init (EVB only).
337 #if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC)
338 /* enable address translation */
342 /* enable and invalidate the data cache */
346 #ifdef CFG_INIT_RAM_LOCK
351 /* set up the stack pointer in our newly created
353 lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
354 ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
356 li r0, 0 /* Make room for stack frame header and */
357 stwu r0, -4(r1) /* clear final stack frame so that */
358 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
360 GET_GOT /* initialize GOT access */
362 /* run low-level CPU init code (from Flash) */
369 /* run 1st part of board init code (from Flash) */
375 .globl invalidate_bats
377 /* invalidate BATs */
391 /* setup_bats - set them up to some initial state */
397 addis r4, r0, CFG_IBAT0L@h
398 ori r4, r4, CFG_IBAT0L@l
399 addis r3, r0, CFG_IBAT0U@h
400 ori r3, r3, CFG_IBAT0U@l
406 addis r4, r0, CFG_DBAT0L@h
407 ori r4, r4, CFG_DBAT0L@l
408 addis r3, r0, CFG_DBAT0U@h
409 ori r3, r3, CFG_DBAT0U@l
415 addis r4, r0, CFG_IBAT1L@h
416 ori r4, r4, CFG_IBAT1L@l
417 addis r3, r0, CFG_IBAT1U@h
418 ori r3, r3, CFG_IBAT1U@l
424 addis r4, r0, CFG_DBAT1L@h
425 ori r4, r4, CFG_DBAT1L@l
426 addis r3, r0, CFG_DBAT1U@h
427 ori r3, r3, CFG_DBAT1U@l
433 addis r4, r0, CFG_IBAT2L@h
434 ori r4, r4, CFG_IBAT2L@l
435 addis r3, r0, CFG_IBAT2U@h
436 ori r3, r3, CFG_IBAT2U@l
442 addis r4, r0, CFG_DBAT2L@h
443 ori r4, r4, CFG_DBAT2L@l
444 addis r3, r0, CFG_DBAT2U@h
445 ori r3, r3, CFG_DBAT2U@l
451 addis r4, r0, CFG_IBAT3L@h
452 ori r4, r4, CFG_IBAT3L@l
453 addis r3, r0, CFG_IBAT3U@h
454 ori r3, r3, CFG_IBAT3U@l
460 addis r4, r0, CFG_DBAT3L@h
461 ori r4, r4, CFG_DBAT3L@l
462 addis r3, r0, CFG_DBAT3U@h
463 ori r3, r3, CFG_DBAT3U@l
468 /* bats are done, now invalidate the TLBs */
471 addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */
484 .globl enable_addr_trans
486 /* enable address translation */
488 ori r5, r5, (MSR_IR | MSR_DR)
493 .globl disable_addr_trans
495 /* disable address translation */
498 andi. r0, r3, (MSR_IR | MSR_DR)
506 * This code finishes saving the registers to the exception frame
507 * and jumps to the appropriate handler for the exception.
508 * Register r21 is pointer into trap frame, r1 has new stack pointer.
510 .globl transfer_to_handler
521 andi. r24,r23,0x3f00 /* get vector offset */
525 mtspr SPRG2,r22 /* r1 is now kernel sp */
526 lwz r24,0(r23) /* virtual address of handler */
527 lwz r23,4(r23) /* where to go when done */
532 rfi /* jump to handler, enable MMU */
535 mfmsr r28 /* Disable interrupts */
539 SYNC /* Some chip revs need this... */
554 lwz r2,_NIP(r1) /* Restore environment */
573 /*-----------------------------------------------------------------------*/
575 * void relocate_code (addr_sp, gd, addr_moni)
577 * This "function" does not return, instead it continues in RAM
578 * after relocating the monitor code.
582 * r5 = length in bytes
587 mr r1, r3 /* Set new stack pointer */
588 mr r9, r4 /* Save copy of Global Data pointer */
589 mr r10, r5 /* Save copy of Destination Address */
591 mr r3, r5 /* Destination Address */
592 lis r4, CFG_MONITOR_BASE@h /* Source Address */
593 ori r4, r4, CFG_MONITOR_BASE@l
594 lwz r5, GOT(__init_end)
596 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
601 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
607 /* First our own GOT */
609 /* then the one used by the C code */
616 bl board_relocate_rom
618 mr r3, r10 /* Destination Address */
619 lis r4, CFG_MONITOR_BASE@h /* Source Address */
620 ori r4, r4, CFG_MONITOR_BASE@l
621 lwz r5, GOT(__init_end)
623 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
628 beq cr1,4f /* In place copy is not necessary */
629 beq 7f /* Protect against 0 count */
648 * Now flush the cache: note that we must start from a cache aligned
649 * address. Otherwise we might miss one cache line.
653 beq 7f /* Always flush prefetch queue in any case */
661 sync /* Wait for all dcbst to complete on bus */
667 7: sync /* Wait for all icbi to complete on bus */
671 * We are done. Do not return, instead branch to second part of board
672 * initialization, now running from RAM.
674 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
683 * Relocation Function, r14 point to got2+0x8000
685 * Adjust got2 pointers, no need to check for 0, this code
686 * already puts a few entries in the table.
688 li r0,__got2_entries@sectoff@l
689 la r3,GOT(_GOT2_TABLE_)
690 lwz r11,GOT(_GOT2_TABLE_)
700 * Now adjust the fixups and the pointers to the fixups
701 * in case we need to move ourselves again.
703 2: li r0,__fixup_entries@sectoff@l
704 lwz r3,GOT(_FIXUP_TABLE_)
718 * Now clear BSS segment
720 lwz r3,GOT(__bss_start)
733 mr r3, r10 /* Destination Address */
734 #ifdef CONFIG_AMIGAONEG3SE
735 mr r4, r9 /* Use RAM copy of the global data */
739 /* not reached - end relocate_code */
740 /*-----------------------------------------------------------------------*/
743 * Copy exception vector code to low memory
746 * r7: source address, r8: end address, r9: target address
751 lwz r8, GOT(_end_of_vectors)
753 li r9, 0x100 /* reset vector always at 0x100 */
756 bgelr /* return if r7>=r8 - just in case */
758 mflr r4 /* save link register */
768 * relocate `hdlr' and `int_return' entries
770 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
771 li r8, Alignment - _start + EXC_OFF_SYS_RESET
774 addi r7, r7, 0x100 /* next exception vector */
778 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
781 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
784 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
785 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
788 addi r7, r7, 0x100 /* next exception vector */
792 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
793 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
796 addi r7, r7, 0x100 /* next exception vector */
800 /* enable execptions from RAM vectors */
806 mtlr r4 /* restore link register */
810 * Function: relocate entries for one exception vector
813 lwz r0, 0(r7) /* hdlr ... */
814 add r0, r0, r3 /* ... += dest_addr */
817 lwz r0, 4(r7) /* int_return ... */
818 add r0, r0, r3 /* ... += dest_addr */
826 #ifdef CFG_INIT_RAM_LOCK
828 /* Allocate Initial RAM in data cache.
830 lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
831 ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
832 li r2, ((CFG_INIT_RAM_END & ~31) + \
833 (CFG_INIT_RAM_ADDR & 31) + 31) / 32
840 /* Lock the data cache */
848 .globl unlock_ram_in_cache
850 /* invalidate the INIT_RAM section */
851 lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
852 ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
853 li r2, ((CFG_INIT_RAM_END & ~31) + \
854 (CFG_INIT_RAM_ADDR & 31) + 31) / 32
859 sync /* Wait for all icbi to complete on bus */
862 /* Unlock the data cache and invalidate it */