3 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * This provides a bit-banged interface to the ethernet MII management
32 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
34 /*****************************************************************************
36 * Read the OUI, manufacture's model number, and revision number.
38 * OUI: 22 bits (unsigned int)
39 * Model: 6 bits (unsigned char)
40 * Revision: 4 bits (unsigned char)
45 int miiphy_info (unsigned char addr,
47 unsigned char *model, unsigned char *rev)
52 * Trick: we are reading two 16 registers into a 32 bit variable
53 * so we do a 16 read into the high order bits of the variable (big
54 * endian, you know), shift it down 16 bits, and the read the rest.
56 if (miiphy_read (addr, PHY_PHYIDR2, (unsigned short *) ®) != 0) {
58 printf ("PHY ID register 2 read failed\n");
65 printf ("PHY_PHYIDR2 @ 0x%x = 0x%04x\n", addr, reg);
68 /* No physical device present at this address */
72 if (miiphy_read (addr, PHY_PHYIDR1, (unsigned short *) ®) != 0) {
74 printf ("PHY ID register 1 read failed\n");
79 printf ("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);
82 *model = (unsigned char) ((reg >> 4) & 0x0000003F);
83 *rev = (unsigned char) ( reg & 0x0000000F);
88 /*****************************************************************************
94 int miiphy_reset (unsigned char addr)
99 if (miiphy_write (addr, PHY_BMCR, 0x8000) != 0) {
101 printf ("PHY reset failed\n");
107 * Poll the control register for the reset bit to go to 0 (it is
108 * auto-clearing). This should happen within 0.5 seconds per the
113 while (((reg & 0x8000) != 0) && (loop_cnt++ < 1000000)) {
114 if (miiphy_read (addr, PHY_BMCR, ®) != 0) {
116 printf ("PHY status read failed\n");
121 if ((reg & 0x8000) == 0) {
124 printf ("PHY reset timed out\n");
131 /*****************************************************************************
133 * Determine the ethernet speed (10/100).
135 int miiphy_speed (unsigned char addr)
139 if (miiphy_read (addr, PHY_ANLPAR, ®)) {
140 printf ("PHY speed1 read failed, assuming 10bT\n");
144 if ((reg & PHY_ANLPAR_100) != 0) {
152 /*****************************************************************************
154 * Determine full/half duplex.
156 int miiphy_duplex (unsigned char addr)
160 if (miiphy_read (addr, PHY_ANLPAR, ®)) {
161 printf ("PHY duplex read failed, assuming half duplex\n");
165 if ((reg & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) != 0) {
172 #endif /* CONFIG_MII || (CONFIG_COMMANDS & CFG_CMD_MII) */