3 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * This provides a bit-banged interface to the ethernet MII management
31 #include <ppc_asm.tmpl>
33 /*****************************************************************************
35 * Utility to send the preamble, address, and register (common to read
38 static void miiphy_pre (char read, unsigned char addr, unsigned char reg)
41 #if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
42 volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
46 * Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
47 * The IEEE spec says this is a PHY optional requirement. The AMD
48 * 79C874 requires one after power up and one after a MII communications
49 * error. This means that we are doing more preambles than we need,
50 * but it is safer and will be much more robust.
55 for (j = 0; j < 32; j++) {
62 /* send the start bit (01) and the read opcode (10) or write (10) */
84 /* send the PHY address */
85 for (j = 0; j < 5; j++) {
87 if ((addr & 0x10) == 0) {
98 /* send the register address */
99 for (j = 0; j < 5; j++) {
101 if ((reg & 0x10) == 0) {
114 /*****************************************************************************
116 * Read a MII PHY register.
121 int bb_miiphy_read (char *devname, unsigned char addr,
122 unsigned char reg, unsigned short *value)
124 short rdreg; /* register working value */
126 #if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
127 volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
130 miiphy_pre (1, addr, reg);
132 /* tri-state our MDIO I/O pin so we can read */
139 /* check the turnaround bit: the PHY should be driving it to zero */
140 if (MDIO_READ != 0) {
141 /* puts ("PHY didn't drive TA low\n"); */
142 for (j = 0; j < 32; j++) {
154 /* read 16 bits of register data, MSB first */
156 for (j = 0; j < 16; j++) {
175 printf ("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, *value);
182 /*****************************************************************************
184 * Write a MII PHY register.
189 int bb_miiphy_write (char *devname, unsigned char addr,
190 unsigned char reg, unsigned short value)
193 #if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
194 volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
197 miiphy_pre (0, addr, reg);
199 /* send the turnaround (10) */
211 /* write 16 bits of register data, MSB first */
212 for (j = 0; j < 16; j++) {
214 if ((value & 0x00008000) == 0) {
226 * Tri-state the MDIO line.