2 * Driver for NAND support, Rick Bronson
3 * borrowed heavily from:
4 * (c) 1999 Machine Vision Holdings, Inc.
5 * (c) 1999, 2000 David Woodhouse <dwmw2@infradead.org>
7 * Added 16-bit nand support
8 * (C) 2004 Texas Instruments
17 #ifdef CONFIG_SHOW_BOOT_PROGRESS
18 # include <status_led.h>
19 # define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
21 # define SHOW_BOOT_PROGRESS(arg)
24 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
26 #include <linux/mtd/nand.h>
27 #include <linux/mtd/nand_ids.h>
28 #include <jffs2/jffs2.h>
30 #ifdef CONFIG_OMAP1510
31 void archflashwp(void *archdata, int wp);
34 #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
37 * Definition of the out of band configuration structure
39 struct nand_oob_config {
40 int ecc_pos[6]; /* position of ECC bytes inside oob */
41 int badblock_pos; /* position of bad block flag inside oob -1 = inactive */
42 int eccvalid_pos; /* position of ECC valid flag inside oob -1 = inactive */
43 } oob_config = { {0}, 0, 0};
48 /* ****************** WARNING *********************
49 * When ALLOW_ERASE_BAD_DEBUG is non-zero the erase command will
50 * erase (or at least attempt to erase) blocks that are marked
51 * bad. This can be very handy if you are _sure_ that the block
52 * is OK, say because you marked a good block bad to test bad
53 * block handling and you are done testing, or if you have
54 * accidentally marked blocks bad.
56 * Erasing factory marked bad blocks is a _bad_ idea. If the
57 * erase succeeds there is no reliable way to find them again,
58 * and attempting to program or erase bad blocks can affect
59 * the data in _other_ (good) blocks.
61 #define ALLOW_ERASE_BAD_DEBUG 0
63 #define CONFIG_MTD_NAND_ECC /* enable ECC */
64 #define CONFIG_MTD_NAND_ECC_JFFS2
66 /* bits for nand_rw() `cmd'; or together as needed */
67 #define NANDRW_READ 0x01
68 #define NANDRW_WRITE 0x00
69 #define NANDRW_JFFS2 0x02
70 #define NANDRW_JFFS2_SKIP 0x04
75 static void nand_print(struct nand_chip *nand);
76 int nand_rw (struct nand_chip* nand, int cmd,
77 size_t start, size_t len,
78 size_t * retlen, u_char * buf);
79 int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean);
80 static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len,
81 size_t * retlen, u_char *buf, u_char *ecc_code);
82 static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len,
83 size_t * retlen, const u_char * buf, u_char * ecc_code);
84 static void nand_print_bad(struct nand_chip *nand);
85 static int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len,
86 size_t * retlen, u_char * buf);
87 static int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len,
88 size_t * retlen, const u_char * buf);
89 static int NanD_WaitReady(struct nand_chip *nand, int ale_wait);
90 #ifdef CONFIG_MTD_NAND_ECC
91 static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc);
92 static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code);
95 struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE] = {{0}};
97 /* Current NAND Device */
98 static int curr_device = -1;
100 /* ------------------------------------------------------------------------- */
102 int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
109 printf ("Usage:\n%s\n", cmdtp->usage);
112 if (strcmp(argv[1],"info") == 0) {
117 for (i=0; i<CFG_MAX_NAND_DEVICE; ++i) {
118 if(nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN)
119 continue; /* list only known devices */
120 printf ("Device %d: ", i);
121 nand_print(&nand_dev_desc[i]);
125 } else if (strcmp(argv[1],"device") == 0) {
126 if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) {
127 puts ("\nno devices available\n");
130 printf ("\nDevice %d: ", curr_device);
131 nand_print(&nand_dev_desc[curr_device]);
134 } else if (strcmp(argv[1],"bad") == 0) {
135 if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) {
136 puts ("\nno devices available\n");
139 printf ("\nDevice %d bad blocks:\n", curr_device);
140 nand_print_bad(&nand_dev_desc[curr_device]);
144 printf ("Usage:\n%s\n", cmdtp->usage);
147 if (strcmp(argv[1],"device") == 0) {
148 int dev = (int)simple_strtoul(argv[2], NULL, 10);
150 printf ("\nDevice %d: ", dev);
151 if (dev >= CFG_MAX_NAND_DEVICE) {
152 puts ("unknown device\n");
155 nand_print(&nand_dev_desc[dev]);
156 /*nand_print (dev);*/
158 if (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN) {
164 puts ("... is now current device\n");
168 else if (strcmp(argv[1],"erase") == 0 && strcmp(argv[2], "clean") == 0) {
169 struct nand_chip* nand = &nand_dev_desc[curr_device];
171 ulong size = nand->totlen;
174 printf ("\nNAND erase: device %d offset %ld, size %ld ... ",
175 curr_device, off, size);
177 ret = nand_erase (nand, off, size, 1);
179 printf("%s\n", ret ? "ERROR" : "OK");
184 printf ("Usage:\n%s\n", cmdtp->usage);
187 /* at least 4 args */
189 if (strncmp(argv[1], "read", 4) == 0 ||
190 strncmp(argv[1], "write", 5) == 0) {
191 ulong addr = simple_strtoul(argv[2], NULL, 16);
192 ulong off = simple_strtoul(argv[3], NULL, 16);
193 ulong size = simple_strtoul(argv[4], NULL, 16);
194 int cmd = (strncmp(argv[1], "read", 4) == 0) ?
195 NANDRW_READ : NANDRW_WRITE;
197 char* cmdtail = strchr(argv[1], '.');
199 if (cmdtail && !strncmp(cmdtail, ".oob", 2)) {
200 /* read out-of-band data */
201 if (cmd & NANDRW_READ) {
202 ret = nand_read_oob(nand_dev_desc + curr_device,
207 ret = nand_write_oob(nand_dev_desc + curr_device,
213 else if (cmdtail && !strncmp(cmdtail, ".jffs2", 2))
214 cmd |= NANDRW_JFFS2; /* skip bad blocks */
215 else if (cmdtail && !strncmp(cmdtail, ".jffs2s", 2)) {
216 cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */
217 if (cmd & NANDRW_READ)
218 cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */
221 /* need ".e" same as ".j" for compatibility with older units */
222 else if (cmdtail && !strcmp(cmdtail, ".e"))
223 cmd |= NANDRW_JFFS2; /* skip bad blocks */
225 #ifdef CFG_NAND_SKIP_BAD_DOT_I
226 /* need ".i" same as ".jffs2s" for compatibility with older units (esd) */
227 /* ".i" for image -> read skips bad block (no 0xff) */
228 else if (cmdtail && !strcmp(cmdtail, ".i"))
229 cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */
230 if (cmd & NANDRW_READ)
231 cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */
232 #endif /* CFG_NAND_SKIP_BAD_DOT_I */
234 printf ("Usage:\n%s\n", cmdtp->usage);
238 printf ("\nNAND %s: device %d offset %ld, size %ld ... ",
239 (cmd & NANDRW_READ) ? "read" : "write",
240 curr_device, off, size);
242 ret = nand_rw(nand_dev_desc + curr_device, cmd, off, size,
243 &total, (u_char*)addr);
245 printf (" %d bytes %s: %s\n", total,
246 (cmd & NANDRW_READ) ? "read" : "written",
247 ret ? "ERROR" : "OK");
250 } else if (strcmp(argv[1],"erase") == 0 &&
251 (argc == 4 || strcmp("clean", argv[2]) == 0)) {
252 int clean = argc == 5;
253 ulong off = simple_strtoul(argv[2 + clean], NULL, 16);
254 ulong size = simple_strtoul(argv[3 + clean], NULL, 16);
257 printf ("\nNAND erase: device %d offset %ld, size %ld ... ",
258 curr_device, off, size);
260 ret = nand_erase (nand_dev_desc + curr_device, off, size, clean);
262 printf("%s\n", ret ? "ERROR" : "OK");
266 printf ("Usage:\n%s\n", cmdtp->usage);
276 "nand - NAND sub-system\n",
277 "info - show available NAND devices\n"
278 "nand device [dev] - show or set current device\n"
279 "nand read[.jffs2[s]] addr off size\n"
280 "nand write[.jffs2] addr off size - read/write `size' bytes starting\n"
281 " at offset `off' to/from memory address `addr'\n"
282 "nand erase [clean] [off size] - erase `size' bytes from\n"
283 " offset `off' (entire device if not specified)\n"
284 "nand bad - show bad blocks\n"
285 "nand read.oob addr off size - read out-of-band data\n"
286 "nand write.oob addr off size - read out-of-band data\n"
289 int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
291 char *boot_device = NULL;
301 addr = CFG_LOAD_ADDR;
302 boot_device = getenv ("bootdevice");
305 addr = simple_strtoul(argv[1], NULL, 16);
306 boot_device = getenv ("bootdevice");
309 addr = simple_strtoul(argv[1], NULL, 16);
310 boot_device = argv[2];
313 addr = simple_strtoul(argv[1], NULL, 16);
314 boot_device = argv[2];
315 offset = simple_strtoul(argv[3], NULL, 16);
318 printf ("Usage:\n%s\n", cmdtp->usage);
319 SHOW_BOOT_PROGRESS (-1);
324 puts ("\n** No boot device **\n");
325 SHOW_BOOT_PROGRESS (-1);
329 dev = simple_strtoul(boot_device, &ep, 16);
331 if ((dev >= CFG_MAX_NAND_DEVICE) ||
332 (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN)) {
333 printf ("\n** Device %d not available\n", dev);
334 SHOW_BOOT_PROGRESS (-1);
338 printf ("\nLoading from device %d: %s at 0x%lx (offset 0x%lx)\n",
339 dev, nand_dev_desc[dev].name, nand_dev_desc[dev].IO_ADDR,
342 if (nand_rw (nand_dev_desc + dev, NANDRW_READ, offset,
343 SECTORSIZE, NULL, (u_char *)addr)) {
344 printf ("** Read error on %d\n", dev);
345 SHOW_BOOT_PROGRESS (-1);
349 hdr = (image_header_t *)addr;
351 if (ntohl(hdr->ih_magic) == IH_MAGIC) {
353 print_image_hdr (hdr);
355 cnt = (ntohl(hdr->ih_size) + sizeof(image_header_t));
358 printf ("\n** Bad Magic Number 0x%x **\n", hdr->ih_magic);
359 SHOW_BOOT_PROGRESS (-1);
363 if (nand_rw (nand_dev_desc + dev, NANDRW_READ, offset + SECTORSIZE, cnt,
364 NULL, (u_char *)(addr+SECTORSIZE))) {
365 printf ("** Read error on %d\n", dev);
366 SHOW_BOOT_PROGRESS (-1);
370 /* Loading ok, update default load address */
374 /* Check if we should attempt an auto-start */
375 if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) {
377 extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
379 local_args[0] = argv[0];
380 local_args[1] = NULL;
382 printf ("Automatic boot of image at addr 0x%08lx ...\n", addr);
384 do_bootm (cmdtp, 0, 1, local_args);
391 nboot, 4, 1, do_nandboot,
392 "nboot - boot from NAND device\n",
396 /* returns 0 if block containing pos is OK:
397 * valid erase block and
398 * not marked bad, or no bad mark position is specified
399 * returns 1 if marked bad or otherwise invalid
401 int check_block (struct nand_chip *nand, unsigned long pos)
405 uint16_t oob_data16[6];
406 int page0 = pos & (-nand->erasesize);
407 int page1 = page0 + nand->oobblock;
408 int badpos = oob_config.badblock_pos;
410 if (pos >= nand->totlen)
414 return 0; /* no way to check, assume OK */
417 if (nand_read_oob(nand, (page0 + 0), 12, &retlen, (uint8_t *)oob_data16)
418 || (oob_data16[2] & 0xff00) != 0xff00)
420 if (nand_read_oob(nand, (page1 + 0), 12, &retlen, (uint8_t *)oob_data16)
421 || (oob_data16[2] & 0xff00) != 0xff00)
424 /* Note - bad block marker can be on first or second page */
425 if (nand_read_oob(nand, page0 + badpos, 1, &retlen, &oob_data)
427 || nand_read_oob (nand, page1 + badpos, 1, &retlen, &oob_data)
435 /* print bad blocks in NAND flash */
436 static void nand_print_bad(struct nand_chip* nand)
440 for (pos = 0; pos < nand->totlen; pos += nand->erasesize) {
441 if (check_block(nand, pos))
442 printf(" 0x%8.8lx\n", pos);
447 /* cmd: 0: NANDRW_WRITE write, fail on bad block
448 * 1: NANDRW_READ read, fail on bad block
449 * 2: NANDRW_WRITE | NANDRW_JFFS2 write, skip bad blocks
450 * 3: NANDRW_READ | NANDRW_JFFS2 read, data all 0xff for bad blocks
451 * 7: NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP read, skip bad blocks
453 int nand_rw (struct nand_chip* nand, int cmd,
454 size_t start, size_t len,
455 size_t * retlen, u_char * buf)
457 int ret = 0, n, total = 0;
459 /* eblk (once set) is the start of the erase block containing the
460 * data being processed.
462 unsigned long eblk = ~0; /* force mismatch on first pass */
463 unsigned long erasesize = nand->erasesize;
466 if ((start & (-erasesize)) != eblk) {
467 /* have crossed into new erase block, deal with
468 * it if it is sure marked bad.
470 eblk = start & (-erasesize); /* start of block */
471 if (check_block(nand, eblk)) {
472 if (cmd == (NANDRW_READ | NANDRW_JFFS2)) {
474 start - eblk < erasesize) {
481 } else if (cmd == (NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP)) {
484 } else if (cmd == (NANDRW_WRITE | NANDRW_JFFS2)) {
494 /* The ECC will not be calculated correctly if
495 less than 512 is written or read */
496 /* Is request at least 512 bytes AND it starts on a proper boundry */
497 if((start != ROUND_DOWN(start, 0x200)) || (len < 0x200))
498 printf("Warning block writes should be at least 512 bytes and start on a 512 byte boundry\n");
500 if (cmd & NANDRW_READ) {
501 ret = nand_read_ecc(nand, start,
502 min(len, eblk + erasesize - start),
503 &n, (u_char*)buf, eccbuf);
505 ret = nand_write_ecc(nand, start,
506 min(len, eblk + erasesize - start),
507 &n, (u_char*)buf, eccbuf);
524 static void nand_print(struct nand_chip *nand)
526 if (nand->numchips > 1) {
527 printf("%s at 0x%lx,\n"
528 "\t %d chips %s, size %d MB, \n"
529 "\t total size %ld MB, sector size %ld kB\n",
530 nand->name, nand->IO_ADDR, nand->numchips,
531 nand->chips_name, 1 << (nand->chipshift - 20),
532 nand->totlen >> 20, nand->erasesize >> 10);
535 printf("%s at 0x%lx (", nand->chips_name, nand->IO_ADDR);
536 print_size(nand->totlen, ", ");
537 print_size(nand->erasesize, " sector)\n");
541 /* ------------------------------------------------------------------------- */
543 static int NanD_WaitReady(struct nand_chip *nand, int ale_wait)
545 /* This is inline, to optimise the common case, where it's ready instantly */
548 #ifdef NAND_NO_RB /* in config file, shorter delays currently wrap accesses */
550 NAND_WAIT_READY(nand); /* do the worst case 25us wait */
553 #else /* has functional r/b signal */
554 NAND_WAIT_READY(nand);
559 /* NanD_Command: Send a flash command to the flash chip */
561 static inline int NanD_Command(struct nand_chip *nand, unsigned char command)
563 unsigned long nandptr = nand->IO_ADDR;
565 /* Assert the CLE (Command Latch Enable) line to the flash chip */
566 NAND_CTL_SETCLE(nandptr);
568 /* Send the command */
569 WRITE_NAND_COMMAND(command, nandptr);
571 /* Lower the CLE line */
572 NAND_CTL_CLRCLE(nandptr);
575 if(command == NAND_CMD_RESET){
577 NanD_Command(nand, NAND_CMD_STATUS);
579 ret_val = READ_NAND(nandptr);/* wait till ready */
580 } while((ret_val & 0x40) != 0x40);
583 return NanD_WaitReady(nand, 0);
586 /* NanD_Address: Set the current address for the flash chip */
588 static int NanD_Address(struct nand_chip *nand, int numbytes, unsigned long ofs)
590 unsigned long nandptr;
593 nandptr = nand->IO_ADDR;
595 /* Assert the ALE (Address Latch Enable) line to the flash chip */
596 NAND_CTL_SETALE(nandptr);
598 /* Send the address */
599 /* Devices with 256-byte page are addressed as:
600 * Column (bits 0-7), Page (bits 8-15, 16-23, 24-31)
601 * there is no device on the market with page256
602 * and more than 24 bits.
603 * Devices with 512-byte page are addressed as:
604 * Column (bits 0-7), Page (bits 9-16, 17-24, 25-31)
605 * 25-31 is sent only if the chip support it.
606 * bit 8 changes the read command to be sent
607 * (NAND_CMD_READ0 or NAND_CMD_READ1).
610 if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE)
611 WRITE_NAND_ADDRESS(ofs, nandptr);
613 ofs = ofs >> nand->page_shift;
615 if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE) {
616 for (i = 0; i < nand->pageadrlen; i++, ofs = ofs >> 8) {
617 WRITE_NAND_ADDRESS(ofs, nandptr);
621 /* Lower the ALE line */
622 NAND_CTL_CLRALE(nandptr);
624 /* Wait for the chip to respond */
625 return NanD_WaitReady(nand, 1);
628 /* NanD_SelectChip: Select a given flash chip within the current floor */
630 static inline int NanD_SelectChip(struct nand_chip *nand, int chip)
632 /* Wait for it to be ready */
633 return NanD_WaitReady(nand, 0);
636 /* NanD_IdentChip: Identify a given NAND chip given {floor,chip} */
638 static int NanD_IdentChip(struct nand_chip *nand, int floor, int chip)
642 NAND_ENABLE_CE(nand); /* set pin low */
644 if (NanD_Command(nand, NAND_CMD_RESET)) {
646 printf("NanD_Command (reset) for %d,%d returned true\n",
649 NAND_DISABLE_CE(nand); /* set pin high */
653 /* Read the NAND chip ID: 1. Send ReadID command */
654 if (NanD_Command(nand, NAND_CMD_READID)) {
656 printf("NanD_Command (ReadID) for %d,%d returned true\n",
659 NAND_DISABLE_CE(nand); /* set pin high */
663 /* Read the NAND chip ID: 2. Send address byte zero */
664 NanD_Address(nand, ADDR_COLUMN, 0);
666 /* Read the manufacturer and device id codes from the device */
668 mfr = READ_NAND(nand->IO_ADDR);
670 id = READ_NAND(nand->IO_ADDR);
672 NAND_DISABLE_CE(nand); /* set pin high */
673 /* No response - return failure */
674 if (mfr == 0xff || mfr == 0) {
676 printf("NanD_Command (ReadID) got %d %d\n", mfr, id);
681 /* Check it's the same as the first chip we identified.
682 * M-Systems say that any given nand_chip device should only
683 * contain _one_ type of flash part, although that's not a
684 * hardware restriction. */
686 if (nand->mfr == mfr && nand->id == id) {
687 return 1; /* This is another the same the first */
689 printf("Flash chip at floor %d, chip %d is different:\n",
694 /* Print and store the manufacturer and ID codes. */
695 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
696 if (mfr == nand_flash_ids[i].manufacture_id &&
697 id == nand_flash_ids[i].model_id) {
699 printf("Flash chip found:\n\t Manufacturer ID: 0x%2.2X, "
700 "Chip ID: 0x%2.2X (%s)\n", mfr, id,
701 nand_flash_ids[i].name);
707 nand_flash_ids[i].chipshift;
708 nand->page256 = nand_flash_ids[i].page256;
711 nand->oobblock = 256;
713 nand->page_shift = 8;
715 nand->oobblock = 512;
717 nand->page_shift = 9;
719 nand->pageadrlen = nand_flash_ids[i].pageadrlen;
720 nand->erasesize = nand_flash_ids[i].erasesize;
721 nand->chips_name = nand_flash_ids[i].name;
722 nand->bus16 = nand_flash_ids[i].bus16;
731 /* We haven't fully identified the chip. Print as much as we know. */
732 printf("Unknown flash chip found: %2.2X %2.2X\n",
739 /* NanD_ScanChips: Find all NAND chips present in a nand_chip, and identify them */
741 static void NanD_ScanChips(struct nand_chip *nand)
744 int numchips[NAND_MAX_FLOORS];
745 int maxchips = NAND_MAX_CHIPS;
753 /* For each floor, find the number of valid chips it contains */
754 for (floor = 0; floor < NAND_MAX_FLOORS; floor++) {
757 for (chip = 0; chip < maxchips && ret != 0; chip++) {
759 ret = NanD_IdentChip(nand, floor, chip);
767 /* If there are none at all that we recognise, bail */
768 if (!nand->numchips) {
770 puts ("No NAND flash chips recognised.\n");
775 /* Allocate an array to hold the information for each chip */
776 nand->chips = malloc(sizeof(struct Nand) * nand->numchips);
778 puts ("No memory for allocating chip info structures\n");
784 /* Fill out the chip array with {floor, chipno} for each
785 * detected chip in the device. */
786 for (floor = 0; floor < NAND_MAX_FLOORS; floor++) {
787 for (chip = 0; chip < numchips[floor]; chip++) {
788 nand->chips[ret].floor = floor;
789 nand->chips[ret].chip = chip;
790 nand->chips[ret].curadr = 0;
791 nand->chips[ret].curmode = 0x50;
796 /* Calculate and print the total size of the device */
797 nand->totlen = nand->numchips * (1 << nand->chipshift);
800 printf("%d flash chips found. Total nand_chip size: %ld MB\n",
801 nand->numchips, nand->totlen >> 20);
805 /* we need to be fast here, 1 us per read translates to 1 second per meg */
806 static void NanD_ReadBuf (struct nand_chip *nand, u_char * data_buf, int cntr)
808 unsigned long nandptr = nand->IO_ADDR;
810 NanD_Command (nand, NAND_CMD_READ0);
816 val = READ_NAND (nandptr);
817 *data_buf++ = val & 0xff;
818 *data_buf++ = val >> 8;
819 val = READ_NAND (nandptr);
820 *data_buf++ = val & 0xff;
821 *data_buf++ = val >> 8;
822 val = READ_NAND (nandptr);
823 *data_buf++ = val & 0xff;
824 *data_buf++ = val >> 8;
825 val = READ_NAND (nandptr);
826 *data_buf++ = val & 0xff;
827 *data_buf++ = val >> 8;
828 val = READ_NAND (nandptr);
829 *data_buf++ = val & 0xff;
830 *data_buf++ = val >> 8;
831 val = READ_NAND (nandptr);
832 *data_buf++ = val & 0xff;
833 *data_buf++ = val >> 8;
834 val = READ_NAND (nandptr);
835 *data_buf++ = val & 0xff;
836 *data_buf++ = val >> 8;
837 val = READ_NAND (nandptr);
838 *data_buf++ = val & 0xff;
839 *data_buf++ = val >> 8;
844 val = READ_NAND (nandptr);
845 *data_buf++ = val & 0xff;
846 *data_buf++ = val >> 8;
851 *data_buf++ = READ_NAND (nandptr);
852 *data_buf++ = READ_NAND (nandptr);
853 *data_buf++ = READ_NAND (nandptr);
854 *data_buf++ = READ_NAND (nandptr);
855 *data_buf++ = READ_NAND (nandptr);
856 *data_buf++ = READ_NAND (nandptr);
857 *data_buf++ = READ_NAND (nandptr);
858 *data_buf++ = READ_NAND (nandptr);
859 *data_buf++ = READ_NAND (nandptr);
860 *data_buf++ = READ_NAND (nandptr);
861 *data_buf++ = READ_NAND (nandptr);
862 *data_buf++ = READ_NAND (nandptr);
863 *data_buf++ = READ_NAND (nandptr);
864 *data_buf++ = READ_NAND (nandptr);
865 *data_buf++ = READ_NAND (nandptr);
866 *data_buf++ = READ_NAND (nandptr);
871 *data_buf++ = READ_NAND (nandptr);
880 static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len,
881 size_t * retlen, u_char *buf, u_char *ecc_code)
885 #ifdef CONFIG_MTD_NAND_ECC
892 /* Do not allow reads past end of device */
893 if ((start + len) > nand->totlen) {
894 printf ("%s: Attempt read beyond end of device %x %x %x\n",
895 __FUNCTION__, (uint) start, (uint) len, (uint) nand->totlen);
900 /* First we calculate the starting page */
901 /*page = shr(start, nand->page_shift);*/
902 page = start >> nand->page_shift;
904 /* Get raw starting column */
905 col = start & (nand->oobblock - 1);
907 /* Initialize return value */
910 /* Select the NAND device */
911 NAND_ENABLE_CE(nand); /* set pin low */
913 /* Loop until all data read */
914 while (*retlen < len) {
916 #ifdef CONFIG_MTD_NAND_ECC
917 /* Do we have this page in cache ? */
918 if (nand->cache_page == page)
920 /* Send the read command */
921 NanD_Command(nand, NAND_CMD_READ0);
923 NanD_Address(nand, ADDR_COLUMN_PAGE,
924 (page << nand->page_shift) + (col >> 1));
926 NanD_Address(nand, ADDR_COLUMN_PAGE,
927 (page << nand->page_shift) + col);
930 /* Read in a page + oob data */
931 NanD_ReadBuf(nand, nand->data_buf, nand->oobblock + nand->oobsize);
933 /* copy data into cache, for read out of cache and if ecc fails */
934 if (nand->data_cache) {
935 memcpy (nand->data_cache, nand->data_buf,
936 nand->oobblock + nand->oobsize);
939 /* Pick the ECC bytes out of the oob data */
940 for (j = 0; j < 6; j++) {
941 ecc_code[j] = nand->data_buf[(nand->oobblock + oob_config.ecc_pos[j])];
944 /* Calculate the ECC and verify it */
945 /* If block was not written with ECC, skip ECC */
946 if (oob_config.eccvalid_pos != -1 &&
947 (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0x0f) != 0x0f) {
949 nand_calculate_ecc (&nand->data_buf[0], &ecc_calc[0]);
950 switch (nand_correct_data (&nand->data_buf[0], &ecc_code[0], &ecc_calc[0])) {
952 printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page);
956 case 2: /* transfer ECC corrected data to cache */
957 if (nand->data_cache)
958 memcpy (nand->data_cache, nand->data_buf, 256);
963 if (oob_config.eccvalid_pos != -1 &&
964 nand->oobblock == 512 && (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0xf0) != 0xf0) {
966 nand_calculate_ecc (&nand->data_buf[256], &ecc_calc[3]);
967 switch (nand_correct_data (&nand->data_buf[256], &ecc_code[3], &ecc_calc[3])) {
969 printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page);
973 case 2: /* transfer ECC corrected data to cache */
974 if (nand->data_cache)
975 memcpy (&nand->data_cache[256], &nand->data_buf[256], 256);
980 /* Read the data from ECC data buffer into return buffer */
981 data_poi = (nand->data_cache) ? nand->data_cache : nand->data_buf;
983 if ((*retlen + (nand->oobblock - col)) >= len) {
984 memcpy (buf + *retlen, data_poi, len - *retlen);
987 memcpy (buf + *retlen, data_poi, nand->oobblock - col);
988 *retlen += nand->oobblock - col;
990 /* Set cache page address, invalidate, if ecc_failed */
991 nand->cache_page = (nand->data_cache && !ecc_failed) ? page : -1;
993 ecc_status += ecc_failed;
997 /* Send the read command */
998 NanD_Command(nand, NAND_CMD_READ0);
1000 NanD_Address(nand, ADDR_COLUMN_PAGE,
1001 (page << nand->page_shift) + (col >> 1));
1003 NanD_Address(nand, ADDR_COLUMN_PAGE,
1004 (page << nand->page_shift) + col);
1007 /* Read the data directly into the return buffer */
1008 if ((*retlen + (nand->oobblock - col)) >= len) {
1009 NanD_ReadBuf(nand, buf + *retlen, len - *retlen);
1014 NanD_ReadBuf(nand, buf + *retlen, nand->oobblock - col);
1015 *retlen += nand->oobblock - col;
1018 /* For subsequent reads align to page boundary. */
1020 /* Increment page address */
1024 /* De-select the NAND device */
1025 NAND_DISABLE_CE(nand); /* set pin high */
1028 * Return success, if no ECC failures, else -EIO
1029 * fs driver will take care of that, because
1030 * retlen == desired len and result == -EIO
1032 return ecc_status ? -1 : 0;
1036 * Nand_page_program function is used for write and writev !
1038 static int nand_write_page (struct nand_chip *nand,
1039 int page, int col, int last, u_char * ecc_code)
1043 unsigned long nandptr = nand->IO_ADDR;
1045 #ifdef CONFIG_MTD_NAND_ECC
1046 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1047 int ecc_bytes = (nand->oobblock == 512) ? 6 : 3;
1051 for (i = nand->oobblock; i < nand->oobblock + nand->oobsize; i++)
1052 nand->data_buf[i] = 0xff;
1054 #ifdef CONFIG_MTD_NAND_ECC
1055 /* Zero out the ECC array */
1056 for (i = 0; i < 6; i++)
1059 /* Read back previous written data, if col > 0 */
1061 NanD_Command (nand, NAND_CMD_READ0);
1063 NanD_Address (nand, ADDR_COLUMN_PAGE,
1064 (page << nand->page_shift) + (col >> 1));
1066 NanD_Address (nand, ADDR_COLUMN_PAGE,
1067 (page << nand->page_shift) + col);
1073 for (i = 0; i < col; i += 2) {
1074 val = READ_NAND (nandptr);
1075 nand->data_buf[i] = val & 0xff;
1076 nand->data_buf[i + 1] = val >> 8;
1079 for (i = 0; i < col; i++)
1080 nand->data_buf[i] = READ_NAND (nandptr);
1084 /* Calculate and write the ECC if we have enough data */
1085 if ((col < nand->eccsize) && (last >= nand->eccsize)) {
1086 nand_calculate_ecc (&nand->data_buf[0], &(ecc_code[0]));
1087 for (i = 0; i < 3; i++) {
1088 nand->data_buf[(nand->oobblock +
1089 oob_config.ecc_pos[i])] = ecc_code[i];
1091 if (oob_config.eccvalid_pos != -1) {
1092 nand->data_buf[nand->oobblock +
1093 oob_config.eccvalid_pos] = 0xf0;
1097 /* Calculate and write the second ECC if we have enough data */
1098 if ((nand->oobblock == 512) && (last == nand->oobblock)) {
1099 nand_calculate_ecc (&nand->data_buf[256], &(ecc_code[3]));
1100 for (i = 3; i < 6; i++) {
1101 nand->data_buf[(nand->oobblock +
1102 oob_config.ecc_pos[i])] = ecc_code[i];
1104 if (oob_config.eccvalid_pos != -1) {
1105 nand->data_buf[nand->oobblock +
1106 oob_config.eccvalid_pos] &= 0x0f;
1110 /* Prepad for partial page programming !!! */
1111 for (i = 0; i < col; i++)
1112 nand->data_buf[i] = 0xff;
1114 /* Postpad for partial page programming !!! oob is already padded */
1115 for (i = last; i < nand->oobblock; i++)
1116 nand->data_buf[i] = 0xff;
1118 /* Send command to begin auto page programming */
1119 NanD_Command (nand, NAND_CMD_READ0);
1120 NanD_Command (nand, NAND_CMD_SEQIN);
1122 NanD_Address (nand, ADDR_COLUMN_PAGE,
1123 (page << nand->page_shift) + (col >> 1));
1125 NanD_Address (nand, ADDR_COLUMN_PAGE,
1126 (page << nand->page_shift) + col);
1129 /* Write out complete page of data */
1131 for (i = 0; i < (nand->oobblock + nand->oobsize); i += 2) {
1132 WRITE_NAND (nand->data_buf[i] +
1133 (nand->data_buf[i + 1] << 8),
1137 for (i = 0; i < (nand->oobblock + nand->oobsize); i++)
1138 WRITE_NAND (nand->data_buf[i], nand->IO_ADDR);
1141 /* Send command to actually program the data */
1142 NanD_Command (nand, NAND_CMD_PAGEPROG);
1143 NanD_Command (nand, NAND_CMD_STATUS);
1149 ret_val = READ_NAND (nandptr); /* wait till ready */
1150 } while ((ret_val & 0x40) != 0x40);
1153 /* See if device thinks it succeeded */
1154 if (READ_NAND (nand->IO_ADDR) & 0x01) {
1155 printf ("%s: Failed write, page 0x%08x, ", __FUNCTION__,
1159 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1161 * The NAND device assumes that it is always writing to
1162 * a cleanly erased page. Hence, it performs its internal
1163 * write verification only on bits that transitioned from
1164 * 1 to 0. The device does NOT verify the whole page on a
1165 * byte by byte basis. It is possible that the page was
1166 * not completely erased or the page is becoming unusable
1167 * due to wear. The read with ECC would catch the error
1168 * later when the ECC page check fails, but we would rather
1169 * catch it early in the page write stage. Better to write
1170 * no data than invalid data.
1173 /* Send command to read back the page */
1174 if (col < nand->eccsize)
1175 NanD_Command (nand, NAND_CMD_READ0);
1177 NanD_Command (nand, NAND_CMD_READ1);
1179 NanD_Address (nand, ADDR_COLUMN_PAGE,
1180 (page << nand->page_shift) + (col >> 1));
1182 NanD_Address (nand, ADDR_COLUMN_PAGE,
1183 (page << nand->page_shift) + col);
1186 /* Loop through and verify the data */
1188 for (i = col; i < last; i = +2) {
1189 if ((nand->data_buf[i] +
1190 (nand->data_buf[i + 1] << 8)) != READ_NAND (nand->IO_ADDR)) {
1191 printf ("%s: Failed write verify, page 0x%08x ",
1192 __FUNCTION__, page);
1197 for (i = col; i < last; i++) {
1198 if (nand->data_buf[i] != READ_NAND (nand->IO_ADDR)) {
1199 printf ("%s: Failed write verify, page 0x%08x ",
1200 __FUNCTION__, page);
1206 #ifdef CONFIG_MTD_NAND_ECC
1208 * We also want to check that the ECC bytes wrote
1209 * correctly for the same reasons stated above.
1211 NanD_Command (nand, NAND_CMD_READOOB);
1213 NanD_Address (nand, ADDR_COLUMN_PAGE,
1214 (page << nand->page_shift) + (col >> 1));
1216 NanD_Address (nand, ADDR_COLUMN_PAGE,
1217 (page << nand->page_shift) + col);
1220 for (i = 0; i < nand->oobsize; i += 2) {
1221 val = READ_NAND (nand->IO_ADDR);
1222 nand->data_buf[i] = val & 0xff;
1223 nand->data_buf[i + 1] = val >> 8;
1226 for (i = 0; i < nand->oobsize; i++) {
1227 nand->data_buf[i] = READ_NAND (nand->IO_ADDR);
1230 for (i = 0; i < ecc_bytes; i++) {
1231 if ((nand->data_buf[(oob_config.ecc_pos[i])] != ecc_code[i]) && ecc_code[i]) {
1232 printf ("%s: Failed ECC write "
1233 "verify, page 0x%08x, "
1234 "%6i bytes were succesful\n",
1235 __FUNCTION__, page, i);
1239 #endif /* CONFIG_MTD_NAND_ECC */
1240 #endif /* CONFIG_MTD_NAND_VERIFY_WRITE */
1244 static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len,
1245 size_t * retlen, const u_char * buf, u_char * ecc_code)
1247 int i, page, col, cnt, ret = 0;
1249 /* Do not allow write past end of device */
1250 if ((to + len) > nand->totlen) {
1251 printf ("%s: Attempt to write past end of page\n", __FUNCTION__);
1255 /* Shift to get page */
1256 page = ((int) to) >> nand->page_shift;
1258 /* Get the starting column */
1259 col = to & (nand->oobblock - 1);
1261 /* Initialize return length value */
1264 /* Select the NAND device */
1265 #ifdef CONFIG_OMAP1510
1272 NAND_ENABLE_CE(nand); /* set pin low */
1274 /* Check the WP bit */
1275 NanD_Command(nand, NAND_CMD_STATUS);
1276 if (!(READ_NAND(nand->IO_ADDR) & 0x80)) {
1277 printf ("%s: Device is write protected!!!\n", __FUNCTION__);
1282 /* Loop until all data is written */
1283 while (*retlen < len) {
1284 /* Invalidate cache, if we write to this page */
1285 if (nand->cache_page == page)
1286 nand->cache_page = -1;
1288 /* Write data into buffer */
1289 if ((col + len) >= nand->oobblock) {
1290 for (i = col, cnt = 0; i < nand->oobblock; i++, cnt++) {
1291 nand->data_buf[i] = buf[(*retlen + cnt)];
1294 for (i = col, cnt = 0; cnt < (len - *retlen); i++, cnt++) {
1295 nand->data_buf[i] = buf[(*retlen + cnt)];
1298 /* We use the same function for write and writev !) */
1299 ret = nand_write_page (nand, page, col, i, ecc_code);
1303 /* Next data start at page boundary */
1306 /* Update written bytes count */
1309 /* Increment page address */
1317 /* De-select the NAND device */
1318 NAND_DISABLE_CE(nand); /* set pin high */
1319 #ifdef CONFIG_OMAP1510
1329 /* read from the 16 bytes of oob data that correspond to a 512 byte
1330 * page or 2 256-byte pages.
1332 static int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len,
1333 size_t * retlen, u_char * buf)
1336 struct Nand *mychip;
1339 mychip = &nand->chips[ofs >> nand->chipshift];
1341 /* update address for 2M x 8bit devices. OOB starts on the second */
1342 /* page to maintain compatibility with nand_read_ecc. */
1343 if (nand->page256) {
1350 NAND_ENABLE_CE(nand); /* set pin low */
1351 NanD_Command(nand, NAND_CMD_READOOB);
1353 NanD_Address(nand, ADDR_COLUMN_PAGE,
1354 ((ofs >> nand->page_shift) << nand->page_shift) +
1355 ((ofs & (nand->oobblock - 1)) >> 1));
1357 NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
1360 /* treat crossing 8-byte OOB data for 2M x 8bit devices */
1361 /* Note: datasheet says it should automaticaly wrap to the */
1362 /* next OOB block, but it didn't work here. mf. */
1363 if (nand->page256 && ofs + len > (ofs | 0x7) + 1) {
1364 len256 = (ofs | 0x7) + 1 - ofs;
1365 NanD_ReadBuf(nand, buf, len256);
1367 NanD_Command(nand, NAND_CMD_READOOB);
1368 NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff));
1371 NanD_ReadBuf(nand, &buf[len256], len - len256);
1374 /* Reading the full OOB data drops us off of the end of the page,
1375 * causing the flash device to go into busy mode, so we need
1376 * to wait until ready 11.4.1 and Toshiba TC58256FT nands */
1378 ret = NanD_WaitReady(nand, 1);
1379 NAND_DISABLE_CE(nand); /* set pin high */
1385 /* write to the 16 bytes of oob data that correspond to a 512 byte
1386 * page or 2 256-byte pages.
1388 static int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len,
1389 size_t * retlen, const u_char * buf)
1393 unsigned long nandptr = nand->IO_ADDR;
1396 printf("nand_write_oob(%lx, %d): %2.2X %2.2X %2.2X %2.2X ... %2.2X %2.2X .. %2.2X %2.2X\n",
1397 (long)ofs, len, buf[0], buf[1], buf[2], buf[3],
1398 buf[8], buf[9], buf[14],buf[15]);
1401 NAND_ENABLE_CE(nand); /* set pin low to enable chip */
1403 /* Reset the chip */
1404 NanD_Command(nand, NAND_CMD_RESET);
1406 /* issue the Read2 command to set the pointer to the Spare Data Area. */
1407 NanD_Command(nand, NAND_CMD_READOOB);
1409 NanD_Address(nand, ADDR_COLUMN_PAGE,
1410 ((ofs >> nand->page_shift) << nand->page_shift) +
1411 ((ofs & (nand->oobblock - 1)) >> 1));
1413 NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
1416 /* update address for 2M x 8bit devices. OOB starts on the second */
1417 /* page to maintain compatibility with nand_read_ecc. */
1418 if (nand->page256) {
1425 /* issue the Serial Data In command to initial the Page Program process */
1426 NanD_Command(nand, NAND_CMD_SEQIN);
1428 NanD_Address(nand, ADDR_COLUMN_PAGE,
1429 ((ofs >> nand->page_shift) << nand->page_shift) +
1430 ((ofs & (nand->oobblock - 1)) >> 1));
1432 NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
1435 /* treat crossing 8-byte OOB data for 2M x 8bit devices */
1436 /* Note: datasheet says it should automaticaly wrap to the */
1437 /* next OOB block, but it didn't work here. mf. */
1438 if (nand->page256 && ofs + len > (ofs | 0x7) + 1) {
1439 len256 = (ofs | 0x7) + 1 - ofs;
1440 for (i = 0; i < len256; i++)
1441 WRITE_NAND(buf[i], nandptr);
1443 NanD_Command(nand, NAND_CMD_PAGEPROG);
1444 NanD_Command(nand, NAND_CMD_STATUS);
1448 ret_val = READ_NAND(nandptr); /* wait till ready */
1449 } while ((ret_val & 0x40) != 0x40);
1452 if (READ_NAND(nandptr) & 1) {
1453 puts ("Error programming oob data\n");
1454 /* There was an error */
1455 NAND_DISABLE_CE(nand); /* set pin high */
1459 NanD_Command(nand, NAND_CMD_SEQIN);
1460 NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff));
1464 for (i = len256; i < len; i += 2) {
1465 WRITE_NAND(buf[i] + (buf[i+1] << 8), nandptr);
1468 for (i = len256; i < len; i++)
1469 WRITE_NAND(buf[i], nandptr);
1472 NanD_Command(nand, NAND_CMD_PAGEPROG);
1473 NanD_Command(nand, NAND_CMD_STATUS);
1477 ret_val = READ_NAND(nandptr); /* wait till ready */
1478 } while ((ret_val & 0x40) != 0x40);
1481 if (READ_NAND(nandptr) & 1) {
1482 puts ("Error programming oob data\n");
1483 /* There was an error */
1484 NAND_DISABLE_CE(nand); /* set pin high */
1489 NAND_DISABLE_CE(nand); /* set pin high */
1495 int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean)
1497 /* This is defined as a structure so it will work on any system
1498 * using native endian jffs2 (the default).
1500 static struct jffs2_unknown_node clean_marker = {
1501 JFFS2_MAGIC_BITMASK,
1502 JFFS2_NODETYPE_CLEANMARKER,
1503 8 /* 8 bytes in this node */
1505 unsigned long nandptr;
1506 struct Nand *mychip;
1509 if (ofs & (nand->erasesize-1) || len & (nand->erasesize-1)) {
1510 printf ("Offset and size must be sector aligned, erasesize = %d\n",
1511 (int) nand->erasesize);
1515 nandptr = nand->IO_ADDR;
1517 /* Select the NAND device */
1518 #ifdef CONFIG_OMAP1510
1524 NAND_ENABLE_CE(nand); /* set pin low */
1526 /* Check the WP bit */
1527 NanD_Command(nand, NAND_CMD_STATUS);
1528 if (!(READ_NAND(nand->IO_ADDR) & 0x80)) {
1529 printf ("nand_write_ecc: Device is write protected!!!\n");
1534 /* Check the WP bit */
1535 NanD_Command(nand, NAND_CMD_STATUS);
1536 if (!(READ_NAND(nand->IO_ADDR) & 0x80)) {
1537 printf ("%s: Device is write protected!!!\n", __FUNCTION__);
1542 /* FIXME: Do nand in the background. Use timers or schedule_task() */
1544 /*mychip = &nand->chips[shr(ofs, nand->chipshift)];*/
1545 mychip = &nand->chips[ofs >> nand->chipshift];
1547 /* always check for bad block first, genuine bad blocks
1548 * should _never_ be erased.
1550 if (ALLOW_ERASE_BAD_DEBUG || !check_block(nand, ofs)) {
1551 /* Select the NAND device */
1552 NAND_ENABLE_CE(nand); /* set pin low */
1554 NanD_Command(nand, NAND_CMD_ERASE1);
1555 NanD_Address(nand, ADDR_PAGE, ofs);
1556 NanD_Command(nand, NAND_CMD_ERASE2);
1558 NanD_Command(nand, NAND_CMD_STATUS);
1563 ret_val = READ_NAND(nandptr); /* wait till ready */
1564 } while ((ret_val & 0x40) != 0x40);
1567 if (READ_NAND(nandptr) & 1) {
1568 printf ("%s: Error erasing at 0x%lx\n",
1569 __FUNCTION__, (long)ofs);
1570 /* There was an error */
1575 int n; /* return value not used */
1578 /* clean marker position and size depend
1579 * on the page size, since 256 byte pages
1580 * only have 8 bytes of oob data
1582 if (nand->page256) {
1583 p = NAND_JFFS2_OOB8_FSDAPOS;
1584 l = NAND_JFFS2_OOB8_FSDALEN;
1586 p = NAND_JFFS2_OOB16_FSDAPOS;
1587 l = NAND_JFFS2_OOB16_FSDALEN;
1590 ret = nand_write_oob(nand, ofs + p, l, &n,
1591 (u_char *)&clean_marker);
1592 /* quit here if write failed */
1597 ofs += nand->erasesize;
1598 len -= nand->erasesize;
1602 /* De-select the NAND device */
1603 NAND_DISABLE_CE(nand); /* set pin high */
1604 #ifdef CONFIG_OMAP1510
1614 static inline int nandcheck(unsigned long potential, unsigned long physadr)
1619 unsigned long nand_probe(unsigned long physadr)
1621 struct nand_chip *nand = NULL;
1622 int i = 0, ChipID = 1;
1624 #ifdef CONFIG_MTD_NAND_ECC_JFFS2
1625 oob_config.ecc_pos[0] = NAND_JFFS2_OOB_ECCPOS0;
1626 oob_config.ecc_pos[1] = NAND_JFFS2_OOB_ECCPOS1;
1627 oob_config.ecc_pos[2] = NAND_JFFS2_OOB_ECCPOS2;
1628 oob_config.ecc_pos[3] = NAND_JFFS2_OOB_ECCPOS3;
1629 oob_config.ecc_pos[4] = NAND_JFFS2_OOB_ECCPOS4;
1630 oob_config.ecc_pos[5] = NAND_JFFS2_OOB_ECCPOS5;
1631 oob_config.eccvalid_pos = 4;
1633 oob_config.ecc_pos[0] = NAND_NOOB_ECCPOS0;
1634 oob_config.ecc_pos[1] = NAND_NOOB_ECCPOS1;
1635 oob_config.ecc_pos[2] = NAND_NOOB_ECCPOS2;
1636 oob_config.ecc_pos[3] = NAND_NOOB_ECCPOS3;
1637 oob_config.ecc_pos[4] = NAND_NOOB_ECCPOS4;
1638 oob_config.ecc_pos[5] = NAND_NOOB_ECCPOS5;
1639 oob_config.eccvalid_pos = NAND_NOOB_ECCVPOS;
1641 oob_config.badblock_pos = 5;
1643 for (i=0; i<CFG_MAX_NAND_DEVICE; i++) {
1644 if (nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN) {
1645 nand = &nand_dev_desc[i];
1652 memset((char *)nand, 0, sizeof(struct nand_chip));
1654 nand->IO_ADDR = physadr;
1655 nand->cache_page = -1; /* init the cache page */
1656 NanD_ScanChips(nand);
1658 if (nand->totlen == 0) {
1659 /* no chips found, clean up and quit */
1660 memset((char *)nand, 0, sizeof(struct nand_chip));
1661 nand->ChipID = NAND_ChipID_UNKNOWN;
1665 nand->ChipID = ChipID;
1666 if (curr_device == -1)
1669 nand->data_buf = malloc (nand->oobblock + nand->oobsize);
1670 if (!nand->data_buf) {
1671 puts ("Cannot allocate memory for data structures.\n");
1675 return (nand->totlen);
1678 #ifdef CONFIG_MTD_NAND_ECC
1680 * Pre-calculated 256-way 1 byte column parity
1682 static const u_char nand_ecc_precalc_table[] = {
1683 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a,
1684 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00,
1685 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f,
1686 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
1687 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c,
1688 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
1689 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59,
1690 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
1691 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33,
1692 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
1693 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56,
1694 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
1695 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55,
1696 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
1697 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30,
1698 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
1699 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30,
1700 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
1701 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55,
1702 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
1703 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56,
1704 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
1705 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33,
1706 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
1707 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59,
1708 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
1709 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c,
1710 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
1711 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f,
1712 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
1713 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a,
1714 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00
1719 * Creates non-inverted ECC code from line parity
1721 static void nand_trans_result(u_char reg2, u_char reg3,
1724 u_char a, b, i, tmp1, tmp2;
1726 /* Initialize variables */
1730 /* Calculate first ECC byte */
1731 for (i = 0; i < 4; i++) {
1732 if (reg3 & a) /* LP15,13,11,9 --> ecc_code[0] */
1735 if (reg2 & a) /* LP14,12,10,8 --> ecc_code[0] */
1741 /* Calculate second ECC byte */
1743 for (i = 0; i < 4; i++) {
1744 if (reg3 & a) /* LP7,5,3,1 --> ecc_code[1] */
1747 if (reg2 & a) /* LP6,4,2,0 --> ecc_code[1] */
1753 /* Store two of the ECC bytes */
1759 * Calculate 3 byte ECC code for 256 byte block
1761 static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code)
1763 u_char idx, reg1, reg3;
1766 /* Initialize variables */
1768 ecc_code[0] = ecc_code[1] = ecc_code[2] = 0;
1770 /* Build up column parity */
1771 for(j = 0; j < 256; j++) {
1773 /* Get CP0 - CP5 from table */
1774 idx = nand_ecc_precalc_table[dat[j]];
1777 /* All bit XOR = 1 ? */
1783 /* Create non-inverted ECC code from line parity */
1784 nand_trans_result((reg1 & 0x40) ? ~reg3 : reg3, reg3, ecc_code);
1786 /* Calculate final ECC code */
1787 ecc_code[0] = ~ecc_code[0];
1788 ecc_code[1] = ~ecc_code[1];
1789 ecc_code[2] = ((~reg1) << 2) | 0x03;
1793 * Detect and correct a 1 bit error for 256 byte block
1795 static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc)
1797 u_char a, b, c, d1, d2, d3, add, bit, i;
1799 /* Do error detection */
1800 d1 = calc_ecc[0] ^ read_ecc[0];
1801 d2 = calc_ecc[1] ^ read_ecc[1];
1802 d3 = calc_ecc[2] ^ read_ecc[2];
1804 if ((d1 | d2 | d3) == 0) {
1808 a = (d1 ^ (d1 >> 1)) & 0x55;
1809 b = (d2 ^ (d2 >> 1)) & 0x55;
1810 c = (d3 ^ (d3 >> 1)) & 0x54;
1812 /* Found and will correct single bit error in the data */
1813 if ((a == 0x55) && (b == 0x55) && (c == 0x54)) {
1817 for (i=0; i<4; i++) {
1824 for (i=0; i<4; i++) {
1833 for (i=0; i<3; i++) {
1863 /* ECC Code Error Correction */
1864 read_ecc[0] = calc_ecc[0];
1865 read_ecc[1] = calc_ecc[1];
1866 read_ecc[2] = calc_ecc[2];
1870 /* Uncorrectable Error */
1876 /* Should never happen */
1882 #ifdef CONFIG_JFFS2_NAND
1884 int read_jffs2_nand(size_t start, size_t len,
1885 size_t * retlen, u_char * buf, int nanddev)
1887 return nand_rw(nand_dev_desc + nanddev, NANDRW_READ | NANDRW_JFFS2,
1888 start, len, retlen, buf);
1891 #endif /* CONFIG_JFFS2_NAND */
1894 #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */