1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2011 The Chromium OS Authors.
4 * (C) Copyright 2002-2006
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9 * Marius Groeger <mgroeger@sysgo.de>
17 #include <environment.h>
28 #include <status_led.h>
34 #ifdef CONFIG_MACH_TYPE
35 #include <asm/mach-types.h>
37 #if defined(CONFIG_MP) && defined(CONFIG_PPC)
41 #include <asm/sections.h>
43 #include <linux/errno.h>
46 * Pointer to initial global data area
48 * Here we initialize it if needed.
50 #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
51 #undef XTRN_DECLARE_GLOBAL_DATA_PTR
52 #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
53 DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR);
55 DECLARE_GLOBAL_DATA_PTR;
59 * TODO(sjg@chromium.org): IMO this code should be
60 * refactored to a single function, something like:
62 * void led_set_state(enum led_colour_t colour, int on);
64 /************************************************************************
65 * Coloured LED functionality
66 ************************************************************************
67 * May be supplied by boards if desired
69 __weak void coloured_LED_init(void) {}
70 __weak void red_led_on(void) {}
71 __weak void red_led_off(void) {}
72 __weak void green_led_on(void) {}
73 __weak void green_led_off(void) {}
74 __weak void yellow_led_on(void) {}
75 __weak void yellow_led_off(void) {}
76 __weak void blue_led_on(void) {}
77 __weak void blue_led_off(void) {}
80 * Why is gd allocated a register? Prior to reloc it might be better to
81 * just pass it around to each function in this file?
83 * After reloc one could argue that it is hardly used and doesn't need
84 * to be in a register. Or if it is it should perhaps hold pointers to all
85 * global data for all modules, so that post-reloc we can avoid the massive
86 * literal pool we get on ARM. Or perhaps just encourage each module to use
90 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
91 static int init_func_watchdog_init(void)
93 # if defined(CONFIG_HW_WATCHDOG) && \
94 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
95 defined(CONFIG_SH) || \
96 defined(CONFIG_DESIGNWARE_WATCHDOG) || \
97 defined(CONFIG_IMX_WATCHDOG))
99 puts(" Watchdog enabled\n");
106 int init_func_watchdog_reset(void)
112 #endif /* CONFIG_WATCHDOG */
114 __weak void board_add_ram_info(int use_default)
116 /* please define platform specific board_add_ram_info() */
119 static int init_baud_rate(void)
121 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE);
125 static int display_text_info(void)
127 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP)
128 ulong bss_start, bss_end, text_base;
130 bss_start = (ulong)&__bss_start;
131 bss_end = (ulong)&__bss_end;
133 #ifdef CONFIG_SYS_TEXT_BASE
134 text_base = CONFIG_SYS_TEXT_BASE;
136 text_base = CONFIG_SYS_MONITOR_BASE;
139 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
140 text_base, bss_start, bss_end);
146 #ifdef CONFIG_SYSRESET
147 static int print_resetinfo(void)
153 ret = uclass_first_device_err(UCLASS_SYSRESET, &dev);
155 debug("%s: No sysreset device found (error: %d)\n",
157 /* Not all boards have sysreset drivers available during early
158 * boot, so don't fail if one can't be found.
163 if (!sysreset_get_status(dev, status, sizeof(status)))
164 printf("%s", status);
170 #if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU)
171 static int print_cpuinfo(void)
177 ret = uclass_first_device_err(UCLASS_CPU, &dev);
179 debug("%s: Could not get CPU device (err = %d)\n",
184 ret = cpu_get_desc(dev, desc, sizeof(desc));
186 debug("%s: Could not get CPU description (err = %d)\n",
191 printf("CPU: %s\n", desc);
197 static int announce_dram_init(void)
203 static int show_dram_config(void)
205 unsigned long long size;
207 #ifdef CONFIG_NR_DRAM_BANKS
210 debug("\nRAM Configuration:\n");
211 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
212 size += gd->bd->bi_dram[i].size;
213 debug("Bank #%d: %llx ", i,
214 (unsigned long long)(gd->bd->bi_dram[i].start));
216 print_size(gd->bd->bi_dram[i].size, "\n");
224 print_size(size, "");
225 board_add_ram_info(0);
231 __weak int dram_init_banksize(void)
233 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
234 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
235 gd->bd->bi_dram[0].size = get_effective_memsize();
241 #if defined(CONFIG_SYS_I2C)
242 static int init_func_i2c(void)
245 #ifdef CONFIG_SYS_I2C
248 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
255 #if defined(CONFIG_VID)
256 __weak int init_func_vid(void)
262 #if defined(CONFIG_HARD_SPI)
263 static int init_func_spi(void)
272 static int setup_mon_len(void)
274 #if defined(__ARM__) || defined(__MICROBLAZE__)
275 gd->mon_len = (ulong)&__bss_end - (ulong)_start;
276 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP)
277 gd->mon_len = (ulong)&_end - (ulong)_init;
278 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
279 gd->mon_len = CONFIG_SYS_MONITOR_LEN;
280 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV)
281 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
282 #elif defined(CONFIG_SYS_MONITOR_BASE)
283 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
284 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
289 __weak int arch_cpu_init(void)
294 __weak int mach_cpu_init(void)
299 /* Get the top of usable RAM */
300 __weak ulong board_get_usable_ram_top(ulong total_size)
302 #ifdef CONFIG_SYS_SDRAM_BASE
304 * Detect whether we have so much RAM that it goes past the end of our
305 * 32-bit address space. If so, clip the usable RAM so it doesn't.
307 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
309 * Will wrap back to top of 32-bit space when reservations
317 static int setup_dest_addr(void)
319 debug("Monitor len: %08lX\n", gd->mon_len);
321 * Ram is setup, size stored in gd !!
323 debug("Ram size: %08lX\n", (ulong)gd->ram_size);
324 #if defined(CONFIG_SYS_MEM_TOP_HIDE)
326 * Subtract specified amount of memory to hide so that it won't
327 * get "touched" at all by U-Boot. By fixing up gd->ram_size
328 * the Linux kernel should now get passed the now "corrected"
329 * memory size and won't touch it either. This should work
330 * for arch/ppc and arch/powerpc. Only Linux board ports in
331 * arch/powerpc with bootwrapper support, that recalculate the
332 * memory size from the SDRAM controller setup will have to
335 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
337 #ifdef CONFIG_SYS_SDRAM_BASE
338 gd->ram_base = CONFIG_SYS_SDRAM_BASE;
340 gd->ram_top = gd->ram_base + get_effective_memsize();
341 gd->ram_top = board_get_usable_ram_top(gd->mon_len);
342 gd->relocaddr = gd->ram_top;
343 debug("Ram top: %08lX\n", (ulong)gd->ram_top);
344 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
346 * We need to make sure the location we intend to put secondary core
347 * boot code is reserved and not used by any part of u-boot
349 if (gd->relocaddr > determine_mp_bootpg(NULL)) {
350 gd->relocaddr = determine_mp_bootpg(NULL);
351 debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
358 /* reserve protected RAM */
359 static int reserve_pram(void)
363 reg = env_get_ulong("pram", 10, CONFIG_PRAM);
364 gd->relocaddr -= (reg << 10); /* size is in kB */
365 debug("Reserving %ldk for protected RAM at %08lx\n", reg,
369 #endif /* CONFIG_PRAM */
371 /* Round memory pointer down to next 4 kB limit */
372 static int reserve_round_4k(void)
374 gd->relocaddr &= ~(4096 - 1);
379 __weak int reserve_mmu(void)
381 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
382 /* reserve TLB table */
383 gd->arch.tlb_size = PGTABLE_SIZE;
384 gd->relocaddr -= gd->arch.tlb_size;
386 /* round down to next 64 kB limit */
387 gd->relocaddr &= ~(0x10000 - 1);
389 gd->arch.tlb_addr = gd->relocaddr;
390 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
391 gd->arch.tlb_addr + gd->arch.tlb_size);
393 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
395 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten
396 * with location within secure ram.
398 gd->arch.tlb_allocated = gd->arch.tlb_addr;
406 static int reserve_video(void)
408 #ifdef CONFIG_DM_VIDEO
412 addr = gd->relocaddr;
413 ret = video_reserve(&addr);
416 gd->relocaddr = addr;
417 #elif defined(CONFIG_LCD)
418 # ifdef CONFIG_FB_ADDR
419 gd->fb_base = CONFIG_FB_ADDR;
421 /* reserve memory for LCD display (always full pages) */
422 gd->relocaddr = lcd_setmem(gd->relocaddr);
423 gd->fb_base = gd->relocaddr;
424 # endif /* CONFIG_FB_ADDR */
425 #elif defined(CONFIG_VIDEO) && \
426 (!defined(CONFIG_PPC)) && \
427 !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \
428 !defined(CONFIG_M68K)
429 /* reserve memory for video display (always full pages) */
430 gd->relocaddr = video_setmem(gd->relocaddr);
431 gd->fb_base = gd->relocaddr;
437 static int reserve_trace(void)
440 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
441 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
442 debug("Reserving %dk for trace data at: %08lx\n",
443 CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
449 static int reserve_uboot(void)
451 if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
453 * reserve memory for U-Boot code, data & bss
454 * round down to next 4 kB limit
456 gd->relocaddr -= gd->mon_len;
457 gd->relocaddr &= ~(4096 - 1);
458 #if defined(CONFIG_E500) || defined(CONFIG_MIPS)
459 /* round down to next 64 kB limit so that IVPR stays aligned */
460 gd->relocaddr &= ~(65536 - 1);
463 debug("Reserving %ldk for U-Boot at: %08lx\n",
464 gd->mon_len >> 10, gd->relocaddr);
467 gd->start_addr_sp = gd->relocaddr;
472 /* reserve memory for malloc() area */
473 static int reserve_malloc(void)
475 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN;
476 debug("Reserving %dk for malloc() at: %08lx\n",
477 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
481 /* (permanently) allocate a Board Info struct */
482 static int reserve_board(void)
485 gd->start_addr_sp -= sizeof(bd_t);
486 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t));
487 memset(gd->bd, '\0', sizeof(bd_t));
488 debug("Reserving %zu Bytes for Board Info at: %08lx\n",
489 sizeof(bd_t), gd->start_addr_sp);
494 static int setup_machine(void)
496 #ifdef CONFIG_MACH_TYPE
497 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
502 static int reserve_global_data(void)
504 gd->start_addr_sp -= sizeof(gd_t);
505 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
506 debug("Reserving %zu Bytes for Global Data at: %08lx\n",
507 sizeof(gd_t), gd->start_addr_sp);
511 static int reserve_fdt(void)
513 #ifndef CONFIG_OF_EMBED
515 * If the device tree is sitting immediately above our image then we
516 * must relocate it. If it is embedded in the data section, then it
517 * will be relocated with other data.
520 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
522 gd->start_addr_sp -= gd->fdt_size;
523 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
524 debug("Reserving %lu Bytes for FDT at: %08lx\n",
525 gd->fdt_size, gd->start_addr_sp);
532 static int reserve_bootstage(void)
534 #ifdef CONFIG_BOOTSTAGE
535 int size = bootstage_get_size();
537 gd->start_addr_sp -= size;
538 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
539 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
546 __weak int arch_reserve_stacks(void)
551 static int reserve_stacks(void)
553 /* make stack pointer 16-byte aligned */
554 gd->start_addr_sp -= 16;
555 gd->start_addr_sp &= ~0xf;
558 * let the architecture-specific code tailor gd->start_addr_sp and
561 return arch_reserve_stacks();
564 static int reserve_bloblist(void)
566 #ifdef CONFIG_BLOBLIST
567 gd->start_addr_sp -= CONFIG_BLOBLIST_SIZE;
568 gd->new_bloblist = map_sysmem(gd->start_addr_sp, CONFIG_BLOBLIST_SIZE);
574 static int display_new_sp(void)
576 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);
581 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
583 static int setup_board_part1(void)
588 * Save local variables to board info struct
590 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
591 bd->bi_memsize = gd->ram_size; /* size in bytes */
593 #ifdef CONFIG_SYS_SRAM_BASE
594 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
595 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
598 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
599 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
601 #if defined(CONFIG_M68K)
602 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
604 #if defined(CONFIG_MPC83xx)
605 bd->bi_immrbar = CONFIG_SYS_IMMR;
612 #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
613 static int setup_board_part2(void)
617 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
618 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
619 #if defined(CONFIG_CPM2)
620 bd->bi_cpmfreq = gd->arch.cpm_clk;
621 bd->bi_brgfreq = gd->arch.brg_clk;
622 bd->bi_sccfreq = gd->arch.scc_clk;
623 bd->bi_vco = gd->arch.vco_out;
624 #endif /* CONFIG_CPM2 */
625 #if defined(CONFIG_M68K) && defined(CONFIG_PCI)
626 bd->bi_pcifreq = gd->pci_clk;
628 #if defined(CONFIG_EXTRA_CLOCK)
629 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */
630 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
631 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
639 static int init_post(void)
641 post_bootmode_init();
642 post_run(NULL, POST_ROM | post_bootmode_get(0));
648 static int reloc_fdt(void)
650 #ifndef CONFIG_OF_EMBED
651 if (gd->flags & GD_FLG_SKIP_RELOC)
654 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size);
655 gd->fdt_blob = gd->new_fdt;
662 static int reloc_bootstage(void)
664 #ifdef CONFIG_BOOTSTAGE
665 if (gd->flags & GD_FLG_SKIP_RELOC)
667 if (gd->new_bootstage) {
668 int size = bootstage_get_size();
670 debug("Copying bootstage from %p to %p, size %x\n",
671 gd->bootstage, gd->new_bootstage, size);
672 memcpy(gd->new_bootstage, gd->bootstage, size);
673 gd->bootstage = gd->new_bootstage;
680 static int reloc_bloblist(void)
682 #ifdef CONFIG_BLOBLIST
683 if (gd->flags & GD_FLG_SKIP_RELOC)
685 if (gd->new_bloblist) {
686 int size = CONFIG_BLOBLIST_SIZE;
688 debug("Copying bloblist from %p to %p, size %x\n",
689 gd->bloblist, gd->new_bloblist, size);
690 memcpy(gd->new_bloblist, gd->bloblist, size);
691 gd->bloblist = gd->new_bloblist;
698 static int setup_reloc(void)
700 if (gd->flags & GD_FLG_SKIP_RELOC) {
701 debug("Skipping relocation due to flag\n");
705 #ifdef CONFIG_SYS_TEXT_BASE
707 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
708 #elif defined(CONFIG_M68K)
710 * On all ColdFire arch cpu, monitor code starts always
711 * just after the default vector table location, so at 0x400
713 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
715 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
718 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
720 debug("Relocation Offset is: %08lx\n", gd->reloc_off);
721 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
722 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
728 #ifdef CONFIG_OF_BOARD_FIXUP
729 static int fix_fdt(void)
731 return board_fix_fdt((void *)gd->fdt_blob);
735 /* ARM calls relocate_code from its crt0.S */
736 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
737 !CONFIG_IS_ENABLED(X86_64)
739 static int jump_to_copy(void)
741 if (gd->flags & GD_FLG_SKIP_RELOC)
744 * x86 is special, but in a nice way. It uses a trampoline which
745 * enables the dcache if possible.
747 * For now, other archs use relocate_code(), which is implemented
748 * similarly for all archs. When we do generic relocation, hopefully
749 * we can make all archs enable the dcache prior to relocation.
751 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
753 * SDRAM and console are now initialised. The final stack can now
754 * be setup in SDRAM. Code execution will continue in Flash, but
755 * with the stack in SDRAM and Global Data in temporary memory
758 arch_setup_gd(gd->new_gd);
759 board_init_f_r_trampoline(gd->start_addr_sp);
761 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
768 /* Record the board_init_f() bootstage (after arch_cpu_init()) */
769 static int initf_bootstage(void)
771 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) &&
772 IS_ENABLED(CONFIG_BOOTSTAGE_STASH);
775 ret = bootstage_init(!from_spl);
779 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR,
780 CONFIG_BOOTSTAGE_STASH_SIZE);
782 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE);
783 if (ret && ret != -ENOENT) {
784 debug("Failed to unstash bootstage: err=%d\n", ret);
789 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
794 static int initf_console_record(void)
796 #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN)
797 return console_record_init();
803 static int initf_dm(void)
805 #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN)
808 bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f");
809 ret = dm_init_and_scan(true);
810 bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F);
814 #ifdef CONFIG_TIMER_EARLY
815 ret = dm_timer_init();
823 /* Architecture-specific memory reservation */
824 __weak int reserve_arch(void)
829 __weak int arch_cpu_init_dm(void)
834 static const init_fnc_t init_sequence_f[] = {
836 #ifdef CONFIG_OF_CONTROL
844 initf_bootstage, /* uses its own timer, so does not need DM */
845 #ifdef CONFIG_BLOBLIST
848 initf_console_record,
849 #if defined(CONFIG_HAVE_FSP)
852 arch_cpu_init, /* basic arch cpu dependent setup */
853 mach_cpu_init, /* SoC/machine dependent CPU setup */
856 #if defined(CONFIG_BOARD_EARLY_INIT_F)
859 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
860 /* get CPU and bus clocks according to the environment variable */
861 get_clocks, /* get CPU and bus clocks (etc.) */
863 #if !defined(CONFIG_M68K)
864 timer_init, /* initialize timer */
866 #if defined(CONFIG_BOARD_POSTCLK_INIT)
869 env_init, /* initialize environment */
870 init_baud_rate, /* initialze baudrate settings */
871 serial_init, /* serial communications setup */
872 console_init_f, /* stage 1 init of console */
873 display_options, /* say that we are here */
874 display_text_info, /* show debugging info if required */
875 #if defined(CONFIG_PPC) || defined(CONFIG_SH) || defined(CONFIG_X86)
878 #if defined(CONFIG_SYSRESET)
881 #if defined(CONFIG_DISPLAY_CPUINFO)
882 print_cpuinfo, /* display cpu info (and speed) */
884 #if defined(CONFIG_DTB_RESELECT)
887 #if defined(CONFIG_DISPLAY_BOARDINFO)
890 INIT_FUNC_WATCHDOG_INIT
891 #if defined(CONFIG_MISC_INIT_F)
894 INIT_FUNC_WATCHDOG_RESET
895 #if defined(CONFIG_SYS_I2C)
898 #if defined(CONFIG_VID) && !defined(CONFIG_SPL)
901 #if defined(CONFIG_HARD_SPI)
905 dram_init, /* configure available RAM banks */
909 INIT_FUNC_WATCHDOG_RESET
910 #if defined(CONFIG_SYS_DRAM_TEST)
912 #endif /* CONFIG_SYS_DRAM_TEST */
913 INIT_FUNC_WATCHDOG_RESET
918 INIT_FUNC_WATCHDOG_RESET
920 * Now that we have DRAM mapped and working, we can
921 * relocate the code and continue running from DRAM.
923 * Reserve memory at end of RAM for (top down in that order):
924 * - area that won't get touched by U-Boot and Linux (optional)
925 * - kernel log buffer
929 * - board info struct
953 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
957 #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
958 INIT_FUNC_WATCHDOG_RESET
962 #ifdef CONFIG_OF_BOARD_FIXUP
965 INIT_FUNC_WATCHDOG_RESET
970 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
975 #if defined(CONFIG_XTENSA)
978 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
979 !CONFIG_IS_ENABLED(X86_64)
985 void board_init_f(ulong boot_flags)
987 gd->flags = boot_flags;
988 gd->have_console = 0;
990 if (initcall_run_list(init_sequence_f))
993 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
994 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \
996 /* NOTREACHED - jump_to_copy() does not return */
1001 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
1003 * For now this code is only used on x86.
1005 * init_sequence_f_r is the list of init functions which are run when
1006 * U-Boot is executing from Flash with a semi-limited 'C' environment.
1007 * The following limitations must be considered when implementing an
1009 * - 'static' variables are read-only
1010 * - Global Data (gd->xxx) is read/write
1012 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
1013 * supported). It _should_, if possible, copy global data to RAM and
1014 * initialise the CPU caches (to speed up the relocation process)
1016 * NOTE: At present only x86 uses this route, but it is intended that
1017 * all archs will move to this when generic relocation is implemented.
1019 static const init_fnc_t init_sequence_f_r[] = {
1020 #if !CONFIG_IS_ENABLED(X86_64)
1027 void board_init_f_r(void)
1029 if (initcall_run_list(init_sequence_f_r))
1033 * The pre-relocation drivers may be using memory that has now gone
1034 * away. Mark serial as unavailable - this will fall back to the debug
1035 * UART if available.
1037 * Do the same with log drivers since the memory may not be available.
1039 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY);
1045 * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
1046 * Transfer execution from Flash to RAM by calculating the address
1047 * of the in-RAM copy of board_init_r() and calling it
1049 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
1051 /* NOTREACHED - board_init_r() does not return */
1054 #endif /* CONFIG_X86 */