1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2011 The Chromium OS Authors.
4 * (C) Copyright 2002-2006
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9 * Marius Groeger <mgroeger@sysgo.de>
14 #include <clock_legacy.h>
20 #include <env_internal.h>
37 #include <status_led.h>
43 #ifdef CONFIG_MACH_TYPE
44 #include <asm/mach-types.h>
46 #if defined(CONFIG_MP) && defined(CONFIG_PPC)
50 #include <asm/sections.h>
52 #include <linux/errno.h>
55 * Pointer to initial global data area
57 * Here we initialize it if needed.
59 #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
60 #undef XTRN_DECLARE_GLOBAL_DATA_PTR
61 #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
62 DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR);
64 DECLARE_GLOBAL_DATA_PTR;
68 * TODO(sjg@chromium.org): IMO this code should be
69 * refactored to a single function, something like:
71 * void led_set_state(enum led_colour_t colour, int on);
73 /************************************************************************
74 * Coloured LED functionality
75 ************************************************************************
76 * May be supplied by boards if desired
78 __weak void coloured_LED_init(void) {}
79 __weak void red_led_on(void) {}
80 __weak void red_led_off(void) {}
81 __weak void green_led_on(void) {}
82 __weak void green_led_off(void) {}
83 __weak void yellow_led_on(void) {}
84 __weak void yellow_led_off(void) {}
85 __weak void blue_led_on(void) {}
86 __weak void blue_led_off(void) {}
89 * Why is gd allocated a register? Prior to reloc it might be better to
90 * just pass it around to each function in this file?
92 * After reloc one could argue that it is hardly used and doesn't need
93 * to be in a register. Or if it is it should perhaps hold pointers to all
94 * global data for all modules, so that post-reloc we can avoid the massive
95 * literal pool we get on ARM. Or perhaps just encourage each module to use
99 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
100 static int init_func_watchdog_init(void)
102 # if defined(CONFIG_HW_WATCHDOG) && \
103 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
104 defined(CONFIG_SH) || \
105 defined(CONFIG_DESIGNWARE_WATCHDOG) || \
106 defined(CONFIG_IMX_WATCHDOG))
108 puts(" Watchdog enabled\n");
115 int init_func_watchdog_reset(void)
121 #endif /* CONFIG_WATCHDOG */
123 __weak void board_add_ram_info(int use_default)
125 /* please define platform specific board_add_ram_info() */
128 static int init_baud_rate(void)
130 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE);
134 static int display_text_info(void)
136 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP)
137 ulong bss_start, bss_end, text_base;
139 bss_start = (ulong)&__bss_start;
140 bss_end = (ulong)&__bss_end;
142 #ifdef CONFIG_SYS_TEXT_BASE
143 text_base = CONFIG_SYS_TEXT_BASE;
145 text_base = CONFIG_SYS_MONITOR_BASE;
148 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
149 text_base, bss_start, bss_end);
155 #ifdef CONFIG_SYSRESET
156 static int print_resetinfo(void)
162 ret = uclass_first_device_err(UCLASS_SYSRESET, &dev);
164 debug("%s: No sysreset device found (error: %d)\n",
166 /* Not all boards have sysreset drivers available during early
167 * boot, so don't fail if one can't be found.
172 if (!sysreset_get_status(dev, status, sizeof(status)))
173 printf("%s", status);
179 #if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU)
180 static int print_cpuinfo(void)
186 ret = uclass_first_device_err(UCLASS_CPU, &dev);
188 debug("%s: Could not get CPU device (err = %d)\n",
193 ret = cpu_get_desc(dev, desc, sizeof(desc));
195 debug("%s: Could not get CPU description (err = %d)\n",
200 printf("CPU: %s\n", desc);
206 static int announce_dram_init(void)
212 static int show_dram_config(void)
214 unsigned long long size;
216 #ifdef CONFIG_NR_DRAM_BANKS
219 debug("\nRAM Configuration:\n");
220 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
221 size += gd->bd->bi_dram[i].size;
222 debug("Bank #%d: %llx ", i,
223 (unsigned long long)(gd->bd->bi_dram[i].start));
225 print_size(gd->bd->bi_dram[i].size, "\n");
233 print_size(size, "");
234 board_add_ram_info(0);
240 __weak int dram_init_banksize(void)
242 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
243 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
244 gd->bd->bi_dram[0].size = get_effective_memsize();
250 #if defined(CONFIG_SYS_I2C)
251 static int init_func_i2c(void)
254 #ifdef CONFIG_SYS_I2C
257 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
264 #if defined(CONFIG_VID)
265 __weak int init_func_vid(void)
271 static int setup_mon_len(void)
273 #if defined(__ARM__) || defined(__MICROBLAZE__)
274 gd->mon_len = (ulong)&__bss_end - (ulong)_start;
275 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP)
276 gd->mon_len = (ulong)&_end - (ulong)_init;
277 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
278 gd->mon_len = CONFIG_SYS_MONITOR_LEN;
279 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV)
280 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
281 #elif defined(CONFIG_SYS_MONITOR_BASE)
282 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
283 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
288 static int setup_spl_handoff(void)
290 #if CONFIG_IS_ENABLED(HANDOFF)
291 gd->spl_handoff = bloblist_find(BLOBLISTT_SPL_HANDOFF,
292 sizeof(struct spl_handoff));
293 debug("Found SPL hand-off info %p\n", gd->spl_handoff);
299 __weak int arch_cpu_init(void)
304 __weak int mach_cpu_init(void)
309 /* Get the top of usable RAM */
310 __weak ulong board_get_usable_ram_top(ulong total_size)
312 #ifdef CONFIG_SYS_SDRAM_BASE
314 * Detect whether we have so much RAM that it goes past the end of our
315 * 32-bit address space. If so, clip the usable RAM so it doesn't.
317 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
319 * Will wrap back to top of 32-bit space when reservations
327 static int setup_dest_addr(void)
329 debug("Monitor len: %08lX\n", gd->mon_len);
331 * Ram is setup, size stored in gd !!
333 debug("Ram size: %08lX\n", (ulong)gd->ram_size);
334 #if defined(CONFIG_SYS_MEM_TOP_HIDE)
336 * Subtract specified amount of memory to hide so that it won't
337 * get "touched" at all by U-Boot. By fixing up gd->ram_size
338 * the Linux kernel should now get passed the now "corrected"
339 * memory size and won't touch it either. This should work
340 * for arch/ppc and arch/powerpc. Only Linux board ports in
341 * arch/powerpc with bootwrapper support, that recalculate the
342 * memory size from the SDRAM controller setup will have to
345 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
347 #ifdef CONFIG_SYS_SDRAM_BASE
348 gd->ram_base = CONFIG_SYS_SDRAM_BASE;
350 gd->ram_top = gd->ram_base + get_effective_memsize();
351 gd->ram_top = board_get_usable_ram_top(gd->mon_len);
352 gd->relocaddr = gd->ram_top;
353 debug("Ram top: %08lX\n", (ulong)gd->ram_top);
354 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
356 * We need to make sure the location we intend to put secondary core
357 * boot code is reserved and not used by any part of u-boot
359 if (gd->relocaddr > determine_mp_bootpg(NULL)) {
360 gd->relocaddr = determine_mp_bootpg(NULL);
361 debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
368 /* reserve protected RAM */
369 static int reserve_pram(void)
373 reg = env_get_ulong("pram", 10, CONFIG_PRAM);
374 gd->relocaddr -= (reg << 10); /* size is in kB */
375 debug("Reserving %ldk for protected RAM at %08lx\n", reg,
379 #endif /* CONFIG_PRAM */
381 /* Round memory pointer down to next 4 kB limit */
382 static int reserve_round_4k(void)
384 gd->relocaddr &= ~(4096 - 1);
388 static int reserve_video(void)
390 #ifdef CONFIG_DM_VIDEO
394 addr = gd->relocaddr;
395 ret = video_reserve(&addr);
398 gd->relocaddr = addr;
399 #elif defined(CONFIG_LCD)
400 # ifdef CONFIG_FB_ADDR
401 gd->fb_base = CONFIG_FB_ADDR;
403 /* reserve memory for LCD display (always full pages) */
404 gd->relocaddr = lcd_setmem(gd->relocaddr);
405 gd->fb_base = gd->relocaddr;
406 # endif /* CONFIG_FB_ADDR */
412 static int reserve_trace(void)
415 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
416 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
417 debug("Reserving %luk for trace data at: %08lx\n",
418 (unsigned long)CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
424 static int reserve_uboot(void)
426 if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
428 * reserve memory for U-Boot code, data & bss
429 * round down to next 4 kB limit
431 gd->relocaddr -= gd->mon_len;
432 gd->relocaddr &= ~(4096 - 1);
433 #if defined(CONFIG_E500) || defined(CONFIG_MIPS)
434 /* round down to next 64 kB limit so that IVPR stays aligned */
435 gd->relocaddr &= ~(65536 - 1);
438 debug("Reserving %ldk for U-Boot at: %08lx\n",
439 gd->mon_len >> 10, gd->relocaddr);
442 gd->start_addr_sp = gd->relocaddr;
448 * reserve after start_addr_sp the requested size and make the stack pointer
449 * 16-byte aligned, this alignment is needed for cast on the reserved memory
450 * ref = x86_64 ABI: https://reviews.llvm.org/D30049: 16 bytes
451 * = ARMv8 Instruction Set Overview: quad word, 16 bytes
453 static unsigned long reserve_stack_aligned(size_t size)
455 return ALIGN_DOWN(gd->start_addr_sp - size, 16);
458 #ifdef CONFIG_SYS_NONCACHED_MEMORY
459 static int reserve_noncached(void)
462 * The value of gd->start_addr_sp must match the value of malloc_start
463 * calculated in boatrd_f.c:initr_malloc(), which is passed to
464 * board_r.c:mem_malloc_init() and then used by
465 * cache.c:noncached_init()
467 * These calculations must match the code in cache.c:noncached_init()
469 gd->start_addr_sp = ALIGN(gd->start_addr_sp, MMU_SECTION_SIZE) -
471 gd->start_addr_sp -= ALIGN(CONFIG_SYS_NONCACHED_MEMORY,
473 debug("Reserving %dM for noncached_alloc() at: %08lx\n",
474 CONFIG_SYS_NONCACHED_MEMORY >> 20, gd->start_addr_sp);
480 /* reserve memory for malloc() area */
481 static int reserve_malloc(void)
483 gd->start_addr_sp = reserve_stack_aligned(TOTAL_MALLOC_LEN);
484 debug("Reserving %dk for malloc() at: %08lx\n",
485 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
486 #ifdef CONFIG_SYS_NONCACHED_MEMORY
493 /* (permanently) allocate a Board Info struct */
494 static int reserve_board(void)
497 gd->start_addr_sp = reserve_stack_aligned(sizeof(bd_t));
498 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t));
499 memset(gd->bd, '\0', sizeof(bd_t));
500 debug("Reserving %zu Bytes for Board Info at: %08lx\n",
501 sizeof(bd_t), gd->start_addr_sp);
506 static int setup_machine(void)
508 #ifdef CONFIG_MACH_TYPE
509 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
514 static int reserve_global_data(void)
516 gd->start_addr_sp = reserve_stack_aligned(sizeof(gd_t));
517 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
518 debug("Reserving %zu Bytes for Global Data at: %08lx\n",
519 sizeof(gd_t), gd->start_addr_sp);
523 static int reserve_fdt(void)
525 #ifndef CONFIG_OF_EMBED
527 * If the device tree is sitting immediately above our image then we
528 * must relocate it. If it is embedded in the data section, then it
529 * will be relocated with other data.
532 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
534 gd->start_addr_sp = reserve_stack_aligned(gd->fdt_size);
535 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
536 debug("Reserving %lu Bytes for FDT at: %08lx\n",
537 gd->fdt_size, gd->start_addr_sp);
544 static int reserve_bootstage(void)
546 #ifdef CONFIG_BOOTSTAGE
547 int size = bootstage_get_size();
549 gd->start_addr_sp = reserve_stack_aligned(size);
550 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
551 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
558 __weak int arch_reserve_stacks(void)
563 static int reserve_stacks(void)
565 /* make stack pointer 16-byte aligned */
566 gd->start_addr_sp = reserve_stack_aligned(16);
569 * let the architecture-specific code tailor gd->start_addr_sp and
572 return arch_reserve_stacks();
575 static int reserve_bloblist(void)
577 #ifdef CONFIG_BLOBLIST
578 gd->start_addr_sp = reserve_stack_aligned(CONFIG_BLOBLIST_SIZE);
579 gd->new_bloblist = map_sysmem(gd->start_addr_sp, CONFIG_BLOBLIST_SIZE);
585 static int display_new_sp(void)
587 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);
592 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
594 static int setup_board_part1(void)
599 * Save local variables to board info struct
601 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
602 bd->bi_memsize = gd->ram_size; /* size in bytes */
604 #ifdef CONFIG_SYS_SRAM_BASE
605 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
606 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
609 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
610 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
612 #if defined(CONFIG_M68K)
613 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
615 #if defined(CONFIG_MPC83xx)
616 bd->bi_immrbar = CONFIG_SYS_IMMR;
623 #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
624 static int setup_board_part2(void)
628 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
629 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
630 #if defined(CONFIG_CPM2)
631 bd->bi_cpmfreq = gd->arch.cpm_clk;
632 bd->bi_brgfreq = gd->arch.brg_clk;
633 bd->bi_sccfreq = gd->arch.scc_clk;
634 bd->bi_vco = gd->arch.vco_out;
635 #endif /* CONFIG_CPM2 */
636 #if defined(CONFIG_M68K) && defined(CONFIG_PCI)
637 bd->bi_pcifreq = gd->pci_clk;
639 #if defined(CONFIG_EXTRA_CLOCK)
640 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */
641 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
642 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
650 static int init_post(void)
652 post_bootmode_init();
653 post_run(NULL, POST_ROM | post_bootmode_get(0));
659 static int reloc_fdt(void)
661 #ifndef CONFIG_OF_EMBED
662 if (gd->flags & GD_FLG_SKIP_RELOC)
665 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size);
666 gd->fdt_blob = gd->new_fdt;
673 static int reloc_bootstage(void)
675 #ifdef CONFIG_BOOTSTAGE
676 if (gd->flags & GD_FLG_SKIP_RELOC)
678 if (gd->new_bootstage) {
679 int size = bootstage_get_size();
681 debug("Copying bootstage from %p to %p, size %x\n",
682 gd->bootstage, gd->new_bootstage, size);
683 memcpy(gd->new_bootstage, gd->bootstage, size);
684 gd->bootstage = gd->new_bootstage;
685 bootstage_relocate();
692 static int reloc_bloblist(void)
694 #ifdef CONFIG_BLOBLIST
695 if (gd->flags & GD_FLG_SKIP_RELOC)
697 if (gd->new_bloblist) {
698 int size = CONFIG_BLOBLIST_SIZE;
700 debug("Copying bloblist from %p to %p, size %x\n",
701 gd->bloblist, gd->new_bloblist, size);
702 memcpy(gd->new_bloblist, gd->bloblist, size);
703 gd->bloblist = gd->new_bloblist;
710 static int setup_reloc(void)
712 if (gd->flags & GD_FLG_SKIP_RELOC) {
713 debug("Skipping relocation due to flag\n");
717 #ifdef CONFIG_SYS_TEXT_BASE
719 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
720 #elif defined(CONFIG_M68K)
722 * On all ColdFire arch cpu, monitor code starts always
723 * just after the default vector table location, so at 0x400
725 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
726 #elif !defined(CONFIG_SANDBOX)
727 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
730 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
732 debug("Relocation Offset is: %08lx\n", gd->reloc_off);
733 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
734 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
740 #ifdef CONFIG_OF_BOARD_FIXUP
741 static int fix_fdt(void)
743 return board_fix_fdt((void *)gd->fdt_blob);
747 /* ARM calls relocate_code from its crt0.S */
748 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
749 !CONFIG_IS_ENABLED(X86_64)
751 static int jump_to_copy(void)
753 if (gd->flags & GD_FLG_SKIP_RELOC)
756 * x86 is special, but in a nice way. It uses a trampoline which
757 * enables the dcache if possible.
759 * For now, other archs use relocate_code(), which is implemented
760 * similarly for all archs. When we do generic relocation, hopefully
761 * we can make all archs enable the dcache prior to relocation.
763 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
765 * SDRAM and console are now initialised. The final stack can now
766 * be setup in SDRAM. Code execution will continue in Flash, but
767 * with the stack in SDRAM and Global Data in temporary memory
770 arch_setup_gd(gd->new_gd);
771 board_init_f_r_trampoline(gd->start_addr_sp);
773 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
780 /* Record the board_init_f() bootstage (after arch_cpu_init()) */
781 static int initf_bootstage(void)
783 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) &&
784 IS_ENABLED(CONFIG_BOOTSTAGE_STASH);
787 ret = bootstage_init(!from_spl);
791 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR,
792 CONFIG_BOOTSTAGE_STASH_SIZE);
794 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE);
795 if (ret && ret != -ENOENT) {
796 debug("Failed to unstash bootstage: err=%d\n", ret);
801 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
806 static int initf_console_record(void)
808 #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN)
809 return console_record_init();
815 static int initf_dm(void)
817 #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN)
820 bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f");
821 ret = dm_init_and_scan(true);
822 bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F);
826 #ifdef CONFIG_TIMER_EARLY
827 ret = dm_timer_init();
835 /* Architecture-specific memory reservation */
836 __weak int reserve_arch(void)
841 __weak int arch_cpu_init_dm(void)
846 __weak int checkcpu(void)
851 __weak int clear_bss(void)
856 static const init_fnc_t init_sequence_f[] = {
858 #ifdef CONFIG_OF_CONTROL
861 #ifdef CONFIG_TRACE_EARLY
866 initf_bootstage, /* uses its own timer, so does not need DM */
867 #ifdef CONFIG_BLOBLIST
871 initf_console_record,
872 #if defined(CONFIG_HAVE_FSP)
875 arch_cpu_init, /* basic arch cpu dependent setup */
876 mach_cpu_init, /* SoC/machine dependent CPU setup */
879 #if defined(CONFIG_BOARD_EARLY_INIT_F)
882 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
883 /* get CPU and bus clocks according to the environment variable */
884 get_clocks, /* get CPU and bus clocks (etc.) */
886 #if !defined(CONFIG_M68K)
887 timer_init, /* initialize timer */
889 #if defined(CONFIG_BOARD_POSTCLK_INIT)
892 env_init, /* initialize environment */
893 init_baud_rate, /* initialze baudrate settings */
894 serial_init, /* serial communications setup */
895 console_init_f, /* stage 1 init of console */
896 display_options, /* say that we are here */
897 display_text_info, /* show debugging info if required */
899 #if defined(CONFIG_SYSRESET)
902 #if defined(CONFIG_DISPLAY_CPUINFO)
903 print_cpuinfo, /* display cpu info (and speed) */
905 #if defined(CONFIG_DTB_RESELECT)
908 #if defined(CONFIG_DISPLAY_BOARDINFO)
911 INIT_FUNC_WATCHDOG_INIT
912 #if defined(CONFIG_MISC_INIT_F)
915 INIT_FUNC_WATCHDOG_RESET
916 #if defined(CONFIG_SYS_I2C)
919 #if defined(CONFIG_VID) && !defined(CONFIG_SPL)
923 dram_init, /* configure available RAM banks */
927 INIT_FUNC_WATCHDOG_RESET
928 #if defined(CONFIG_SYS_DRAM_TEST)
930 #endif /* CONFIG_SYS_DRAM_TEST */
931 INIT_FUNC_WATCHDOG_RESET
936 INIT_FUNC_WATCHDOG_RESET
938 * Now that we have DRAM mapped and working, we can
939 * relocate the code and continue running from DRAM.
941 * Reserve memory at end of RAM for (top down in that order):
942 * - area that won't get touched by U-Boot and Linux (optional)
943 * - kernel log buffer
947 * - board info struct
971 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
975 #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
976 INIT_FUNC_WATCHDOG_RESET
980 #ifdef CONFIG_OF_BOARD_FIXUP
983 INIT_FUNC_WATCHDOG_RESET
988 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
993 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
994 !CONFIG_IS_ENABLED(X86_64)
1000 void board_init_f(ulong boot_flags)
1002 gd->flags = boot_flags;
1003 gd->have_console = 0;
1005 if (initcall_run_list(init_sequence_f))
1008 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
1009 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \
1010 !defined(CONFIG_ARC)
1011 /* NOTREACHED - jump_to_copy() does not return */
1016 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
1018 * For now this code is only used on x86.
1020 * init_sequence_f_r is the list of init functions which are run when
1021 * U-Boot is executing from Flash with a semi-limited 'C' environment.
1022 * The following limitations must be considered when implementing an
1024 * - 'static' variables are read-only
1025 * - Global Data (gd->xxx) is read/write
1027 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
1028 * supported). It _should_, if possible, copy global data to RAM and
1029 * initialise the CPU caches (to speed up the relocation process)
1031 * NOTE: At present only x86 uses this route, but it is intended that
1032 * all archs will move to this when generic relocation is implemented.
1034 static const init_fnc_t init_sequence_f_r[] = {
1035 #if !CONFIG_IS_ENABLED(X86_64)
1042 void board_init_f_r(void)
1044 if (initcall_run_list(init_sequence_f_r))
1048 * The pre-relocation drivers may be using memory that has now gone
1049 * away. Mark serial as unavailable - this will fall back to the debug
1050 * UART if available.
1052 * Do the same with log drivers since the memory may not be available.
1054 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY);
1060 * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
1061 * Transfer execution from Flash to RAM by calculating the address
1062 * of the in-RAM copy of board_init_r() and calling it
1064 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
1066 /* NOTREACHED - board_init_r() does not return */
1069 #endif /* CONFIG_X86 */