1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2011 The Chromium OS Authors.
4 * (C) Copyright 2002-2006
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9 * Marius Groeger <mgroeger@sysgo.de>
14 #include <clock_legacy.h>
20 #include <env_internal.h>
37 #include <status_led.h>
43 #include <asm/cache.h>
44 #ifdef CONFIG_MACH_TYPE
45 #include <asm/mach-types.h>
47 #if defined(CONFIG_MP) && defined(CONFIG_PPC)
51 #include <asm/sections.h>
53 #include <linux/errno.h>
56 * Pointer to initial global data area
58 * Here we initialize it if needed.
60 #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
61 #undef XTRN_DECLARE_GLOBAL_DATA_PTR
62 #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
63 DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR);
65 DECLARE_GLOBAL_DATA_PTR;
69 * TODO(sjg@chromium.org): IMO this code should be
70 * refactored to a single function, something like:
72 * void led_set_state(enum led_colour_t colour, int on);
74 /************************************************************************
75 * Coloured LED functionality
76 ************************************************************************
77 * May be supplied by boards if desired
79 __weak void coloured_LED_init(void) {}
80 __weak void red_led_on(void) {}
81 __weak void red_led_off(void) {}
82 __weak void green_led_on(void) {}
83 __weak void green_led_off(void) {}
84 __weak void yellow_led_on(void) {}
85 __weak void yellow_led_off(void) {}
86 __weak void blue_led_on(void) {}
87 __weak void blue_led_off(void) {}
90 * Why is gd allocated a register? Prior to reloc it might be better to
91 * just pass it around to each function in this file?
93 * After reloc one could argue that it is hardly used and doesn't need
94 * to be in a register. Or if it is it should perhaps hold pointers to all
95 * global data for all modules, so that post-reloc we can avoid the massive
96 * literal pool we get on ARM. Or perhaps just encourage each module to use
100 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
101 static int init_func_watchdog_init(void)
103 # if defined(CONFIG_HW_WATCHDOG) && \
104 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
105 defined(CONFIG_SH) || \
106 defined(CONFIG_DESIGNWARE_WATCHDOG) || \
107 defined(CONFIG_IMX_WATCHDOG))
109 puts(" Watchdog enabled\n");
116 int init_func_watchdog_reset(void)
122 #endif /* CONFIG_WATCHDOG */
124 __weak void board_add_ram_info(int use_default)
126 /* please define platform specific board_add_ram_info() */
129 static int init_baud_rate(void)
131 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE);
135 static int display_text_info(void)
137 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP)
138 ulong bss_start, bss_end, text_base;
140 bss_start = (ulong)&__bss_start;
141 bss_end = (ulong)&__bss_end;
143 #ifdef CONFIG_SYS_TEXT_BASE
144 text_base = CONFIG_SYS_TEXT_BASE;
146 text_base = CONFIG_SYS_MONITOR_BASE;
149 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
150 text_base, bss_start, bss_end);
156 #ifdef CONFIG_SYSRESET
157 static int print_resetinfo(void)
163 ret = uclass_first_device_err(UCLASS_SYSRESET, &dev);
165 debug("%s: No sysreset device found (error: %d)\n",
167 /* Not all boards have sysreset drivers available during early
168 * boot, so don't fail if one can't be found.
173 if (!sysreset_get_status(dev, status, sizeof(status)))
174 printf("%s", status);
180 #if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU)
181 static int print_cpuinfo(void)
187 dev = cpu_get_current_dev();
189 debug("%s: Could not get CPU device\n",
194 ret = cpu_get_desc(dev, desc, sizeof(desc));
196 debug("%s: Could not get CPU description (err = %d)\n",
201 printf("CPU: %s\n", desc);
207 static int announce_dram_init(void)
213 static int show_dram_config(void)
215 unsigned long long size;
217 #ifdef CONFIG_NR_DRAM_BANKS
220 debug("\nRAM Configuration:\n");
221 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
222 size += gd->bd->bi_dram[i].size;
223 debug("Bank #%d: %llx ", i,
224 (unsigned long long)(gd->bd->bi_dram[i].start));
226 print_size(gd->bd->bi_dram[i].size, "\n");
234 print_size(size, "");
235 board_add_ram_info(0);
241 __weak int dram_init_banksize(void)
243 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
244 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
245 gd->bd->bi_dram[0].size = get_effective_memsize();
251 #if defined(CONFIG_SYS_I2C)
252 static int init_func_i2c(void)
255 #ifdef CONFIG_SYS_I2C
258 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
265 #if defined(CONFIG_VID)
266 __weak int init_func_vid(void)
272 static int setup_mon_len(void)
274 #if defined(__ARM__) || defined(__MICROBLAZE__)
275 gd->mon_len = (ulong)&__bss_end - (ulong)_start;
276 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP)
277 gd->mon_len = (ulong)&_end - (ulong)_init;
278 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
279 gd->mon_len = CONFIG_SYS_MONITOR_LEN;
280 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV)
281 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
282 #elif defined(CONFIG_SYS_MONITOR_BASE)
283 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
284 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
289 static int setup_spl_handoff(void)
291 #if CONFIG_IS_ENABLED(HANDOFF)
292 gd->spl_handoff = bloblist_find(BLOBLISTT_SPL_HANDOFF,
293 sizeof(struct spl_handoff));
294 debug("Found SPL hand-off info %p\n", gd->spl_handoff);
300 __weak int arch_cpu_init(void)
305 __weak int mach_cpu_init(void)
310 /* Get the top of usable RAM */
311 __weak ulong board_get_usable_ram_top(ulong total_size)
313 #if defined(CONFIG_SYS_SDRAM_BASE) && CONFIG_SYS_SDRAM_BASE > 0
315 * Detect whether we have so much RAM that it goes past the end of our
316 * 32-bit address space. If so, clip the usable RAM so it doesn't.
318 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
320 * Will wrap back to top of 32-bit space when reservations
328 static int setup_dest_addr(void)
330 debug("Monitor len: %08lX\n", gd->mon_len);
332 * Ram is setup, size stored in gd !!
334 debug("Ram size: %08lX\n", (ulong)gd->ram_size);
335 #if defined(CONFIG_SYS_MEM_TOP_HIDE)
337 * Subtract specified amount of memory to hide so that it won't
338 * get "touched" at all by U-Boot. By fixing up gd->ram_size
339 * the Linux kernel should now get passed the now "corrected"
340 * memory size and won't touch it either. This should work
341 * for arch/ppc and arch/powerpc. Only Linux board ports in
342 * arch/powerpc with bootwrapper support, that recalculate the
343 * memory size from the SDRAM controller setup will have to
346 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
348 #ifdef CONFIG_SYS_SDRAM_BASE
349 gd->ram_base = CONFIG_SYS_SDRAM_BASE;
351 gd->ram_top = gd->ram_base + get_effective_memsize();
352 gd->ram_top = board_get_usable_ram_top(gd->mon_len);
353 gd->relocaddr = gd->ram_top;
354 debug("Ram top: %08lX\n", (ulong)gd->ram_top);
355 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
357 * We need to make sure the location we intend to put secondary core
358 * boot code is reserved and not used by any part of u-boot
360 if (gd->relocaddr > determine_mp_bootpg(NULL)) {
361 gd->relocaddr = determine_mp_bootpg(NULL);
362 debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
369 /* reserve protected RAM */
370 static int reserve_pram(void)
374 reg = env_get_ulong("pram", 10, CONFIG_PRAM);
375 gd->relocaddr -= (reg << 10); /* size is in kB */
376 debug("Reserving %ldk for protected RAM at %08lx\n", reg,
380 #endif /* CONFIG_PRAM */
382 /* Round memory pointer down to next 4 kB limit */
383 static int reserve_round_4k(void)
385 gd->relocaddr &= ~(4096 - 1);
389 __weak int arch_reserve_mmu(void)
394 static int reserve_video(void)
396 #ifdef CONFIG_DM_VIDEO
400 addr = gd->relocaddr;
401 ret = video_reserve(&addr);
404 gd->relocaddr = addr;
405 #elif defined(CONFIG_LCD)
406 # ifdef CONFIG_FB_ADDR
407 gd->fb_base = CONFIG_FB_ADDR;
409 /* reserve memory for LCD display (always full pages) */
410 gd->relocaddr = lcd_setmem(gd->relocaddr);
411 gd->fb_base = gd->relocaddr;
412 # endif /* CONFIG_FB_ADDR */
418 static int reserve_trace(void)
421 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
422 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
423 debug("Reserving %luk for trace data at: %08lx\n",
424 (unsigned long)CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
430 static int reserve_uboot(void)
432 if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
434 * reserve memory for U-Boot code, data & bss
435 * round down to next 4 kB limit
437 gd->relocaddr -= gd->mon_len;
438 gd->relocaddr &= ~(4096 - 1);
439 #if defined(CONFIG_E500) || defined(CONFIG_MIPS)
440 /* round down to next 64 kB limit so that IVPR stays aligned */
441 gd->relocaddr &= ~(65536 - 1);
444 debug("Reserving %ldk for U-Boot at: %08lx\n",
445 gd->mon_len >> 10, gd->relocaddr);
448 gd->start_addr_sp = gd->relocaddr;
454 * reserve after start_addr_sp the requested size and make the stack pointer
455 * 16-byte aligned, this alignment is needed for cast on the reserved memory
456 * ref = x86_64 ABI: https://reviews.llvm.org/D30049: 16 bytes
457 * = ARMv8 Instruction Set Overview: quad word, 16 bytes
459 static unsigned long reserve_stack_aligned(size_t size)
461 return ALIGN_DOWN(gd->start_addr_sp - size, 16);
464 #ifdef CONFIG_SYS_NONCACHED_MEMORY
465 static int reserve_noncached(void)
468 * The value of gd->start_addr_sp must match the value of malloc_start
469 * calculated in boatrd_f.c:initr_malloc(), which is passed to
470 * board_r.c:mem_malloc_init() and then used by
471 * cache.c:noncached_init()
473 * These calculations must match the code in cache.c:noncached_init()
475 gd->start_addr_sp = ALIGN(gd->start_addr_sp, MMU_SECTION_SIZE) -
477 gd->start_addr_sp -= ALIGN(CONFIG_SYS_NONCACHED_MEMORY,
479 debug("Reserving %dM for noncached_alloc() at: %08lx\n",
480 CONFIG_SYS_NONCACHED_MEMORY >> 20, gd->start_addr_sp);
486 /* reserve memory for malloc() area */
487 static int reserve_malloc(void)
489 gd->start_addr_sp = reserve_stack_aligned(TOTAL_MALLOC_LEN);
490 debug("Reserving %dk for malloc() at: %08lx\n",
491 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
492 #ifdef CONFIG_SYS_NONCACHED_MEMORY
499 /* (permanently) allocate a Board Info struct */
500 static int reserve_board(void)
503 gd->start_addr_sp = reserve_stack_aligned(sizeof(bd_t));
504 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t));
505 memset(gd->bd, '\0', sizeof(bd_t));
506 debug("Reserving %zu Bytes for Board Info at: %08lx\n",
507 sizeof(bd_t), gd->start_addr_sp);
512 static int setup_machine(void)
514 #ifdef CONFIG_MACH_TYPE
515 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
520 static int reserve_global_data(void)
522 gd->start_addr_sp = reserve_stack_aligned(sizeof(gd_t));
523 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
524 debug("Reserving %zu Bytes for Global Data at: %08lx\n",
525 sizeof(gd_t), gd->start_addr_sp);
529 static int reserve_fdt(void)
531 #ifndef CONFIG_OF_EMBED
533 * If the device tree is sitting immediately above our image then we
534 * must relocate it. If it is embedded in the data section, then it
535 * will be relocated with other data.
538 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
540 gd->start_addr_sp = reserve_stack_aligned(gd->fdt_size);
541 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
542 debug("Reserving %lu Bytes for FDT at: %08lx\n",
543 gd->fdt_size, gd->start_addr_sp);
550 static int reserve_bootstage(void)
552 #ifdef CONFIG_BOOTSTAGE
553 int size = bootstage_get_size();
555 gd->start_addr_sp = reserve_stack_aligned(size);
556 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
557 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
564 __weak int arch_reserve_stacks(void)
569 static int reserve_stacks(void)
571 /* make stack pointer 16-byte aligned */
572 gd->start_addr_sp = reserve_stack_aligned(16);
575 * let the architecture-specific code tailor gd->start_addr_sp and
578 return arch_reserve_stacks();
581 static int reserve_bloblist(void)
583 #ifdef CONFIG_BLOBLIST
584 gd->start_addr_sp = reserve_stack_aligned(CONFIG_BLOBLIST_SIZE);
585 gd->new_bloblist = map_sysmem(gd->start_addr_sp, CONFIG_BLOBLIST_SIZE);
591 static int display_new_sp(void)
593 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);
598 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
600 static int setup_board_part1(void)
605 * Save local variables to board info struct
607 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
608 bd->bi_memsize = gd->ram_size; /* size in bytes */
610 #ifdef CONFIG_SYS_SRAM_BASE
611 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
612 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
615 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
616 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
618 #if defined(CONFIG_M68K)
619 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
621 #if defined(CONFIG_MPC83xx)
622 bd->bi_immrbar = CONFIG_SYS_IMMR;
629 #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
630 static int setup_board_part2(void)
634 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
635 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
636 #if defined(CONFIG_CPM2)
637 bd->bi_cpmfreq = gd->arch.cpm_clk;
638 bd->bi_brgfreq = gd->arch.brg_clk;
639 bd->bi_sccfreq = gd->arch.scc_clk;
640 bd->bi_vco = gd->arch.vco_out;
641 #endif /* CONFIG_CPM2 */
642 #if defined(CONFIG_M68K) && defined(CONFIG_PCI)
643 bd->bi_pcifreq = gd->pci_clk;
645 #if defined(CONFIG_EXTRA_CLOCK)
646 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */
647 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
648 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
656 static int init_post(void)
658 post_bootmode_init();
659 post_run(NULL, POST_ROM | post_bootmode_get(0));
665 static int reloc_fdt(void)
667 #ifndef CONFIG_OF_EMBED
668 if (gd->flags & GD_FLG_SKIP_RELOC)
671 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size);
672 gd->fdt_blob = gd->new_fdt;
679 static int reloc_bootstage(void)
681 #ifdef CONFIG_BOOTSTAGE
682 if (gd->flags & GD_FLG_SKIP_RELOC)
684 if (gd->new_bootstage) {
685 int size = bootstage_get_size();
687 debug("Copying bootstage from %p to %p, size %x\n",
688 gd->bootstage, gd->new_bootstage, size);
689 memcpy(gd->new_bootstage, gd->bootstage, size);
690 gd->bootstage = gd->new_bootstage;
691 bootstage_relocate();
698 static int reloc_bloblist(void)
700 #ifdef CONFIG_BLOBLIST
701 if (gd->flags & GD_FLG_SKIP_RELOC)
703 if (gd->new_bloblist) {
704 int size = CONFIG_BLOBLIST_SIZE;
706 debug("Copying bloblist from %p to %p, size %x\n",
707 gd->bloblist, gd->new_bloblist, size);
708 memcpy(gd->new_bloblist, gd->bloblist, size);
709 gd->bloblist = gd->new_bloblist;
716 static int setup_reloc(void)
718 if (gd->flags & GD_FLG_SKIP_RELOC) {
719 debug("Skipping relocation due to flag\n");
723 #ifdef CONFIG_SYS_TEXT_BASE
725 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
726 #elif defined(CONFIG_M68K)
728 * On all ColdFire arch cpu, monitor code starts always
729 * just after the default vector table location, so at 0x400
731 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
732 #elif !defined(CONFIG_SANDBOX)
733 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
736 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
738 debug("Relocation Offset is: %08lx\n", gd->reloc_off);
739 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
740 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
746 #ifdef CONFIG_OF_BOARD_FIXUP
747 static int fix_fdt(void)
749 return board_fix_fdt((void *)gd->fdt_blob);
753 /* ARM calls relocate_code from its crt0.S */
754 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
755 !CONFIG_IS_ENABLED(X86_64)
757 static int jump_to_copy(void)
759 if (gd->flags & GD_FLG_SKIP_RELOC)
762 * x86 is special, but in a nice way. It uses a trampoline which
763 * enables the dcache if possible.
765 * For now, other archs use relocate_code(), which is implemented
766 * similarly for all archs. When we do generic relocation, hopefully
767 * we can make all archs enable the dcache prior to relocation.
769 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
771 * SDRAM and console are now initialised. The final stack can now
772 * be setup in SDRAM. Code execution will continue in Flash, but
773 * with the stack in SDRAM and Global Data in temporary memory
776 arch_setup_gd(gd->new_gd);
777 board_init_f_r_trampoline(gd->start_addr_sp);
779 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
786 /* Record the board_init_f() bootstage (after arch_cpu_init()) */
787 static int initf_bootstage(void)
789 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) &&
790 IS_ENABLED(CONFIG_BOOTSTAGE_STASH);
793 ret = bootstage_init(!from_spl);
797 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR,
798 CONFIG_BOOTSTAGE_STASH_SIZE);
800 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE);
801 if (ret && ret != -ENOENT) {
802 debug("Failed to unstash bootstage: err=%d\n", ret);
807 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
812 static int initf_console_record(void)
814 #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN)
815 return console_record_init();
821 static int initf_dm(void)
823 #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN)
826 bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f");
827 ret = dm_init_and_scan(true);
828 bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F);
832 #ifdef CONFIG_TIMER_EARLY
833 ret = dm_timer_init();
841 /* Architecture-specific memory reservation */
842 __weak int reserve_arch(void)
847 __weak int arch_cpu_init_dm(void)
852 __weak int checkcpu(void)
857 __weak int clear_bss(void)
862 static const init_fnc_t init_sequence_f[] = {
864 #ifdef CONFIG_OF_CONTROL
867 #ifdef CONFIG_TRACE_EARLY
872 initf_bootstage, /* uses its own timer, so does not need DM */
873 #ifdef CONFIG_BLOBLIST
877 initf_console_record,
878 #if defined(CONFIG_HAVE_FSP)
881 arch_cpu_init, /* basic arch cpu dependent setup */
882 mach_cpu_init, /* SoC/machine dependent CPU setup */
885 #if defined(CONFIG_BOARD_EARLY_INIT_F)
888 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
889 /* get CPU and bus clocks according to the environment variable */
890 get_clocks, /* get CPU and bus clocks (etc.) */
892 #if !defined(CONFIG_M68K)
893 timer_init, /* initialize timer */
895 #if defined(CONFIG_BOARD_POSTCLK_INIT)
898 env_init, /* initialize environment */
899 init_baud_rate, /* initialze baudrate settings */
900 serial_init, /* serial communications setup */
901 console_init_f, /* stage 1 init of console */
902 display_options, /* say that we are here */
903 display_text_info, /* show debugging info if required */
905 #if defined(CONFIG_SYSRESET)
908 #if defined(CONFIG_DISPLAY_CPUINFO)
909 print_cpuinfo, /* display cpu info (and speed) */
911 #if defined(CONFIG_DTB_RESELECT)
914 #if defined(CONFIG_DISPLAY_BOARDINFO)
917 INIT_FUNC_WATCHDOG_INIT
918 #if defined(CONFIG_MISC_INIT_F)
921 INIT_FUNC_WATCHDOG_RESET
922 #if defined(CONFIG_SYS_I2C)
925 #if defined(CONFIG_VID) && !defined(CONFIG_SPL)
929 dram_init, /* configure available RAM banks */
933 INIT_FUNC_WATCHDOG_RESET
934 #if defined(CONFIG_SYS_DRAM_TEST)
936 #endif /* CONFIG_SYS_DRAM_TEST */
937 INIT_FUNC_WATCHDOG_RESET
942 INIT_FUNC_WATCHDOG_RESET
944 * Now that we have DRAM mapped and working, we can
945 * relocate the code and continue running from DRAM.
947 * Reserve memory at end of RAM for (top down in that order):
948 * - area that won't get touched by U-Boot and Linux (optional)
949 * - kernel log buffer
953 * - board info struct
975 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
979 #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
980 INIT_FUNC_WATCHDOG_RESET
984 #ifdef CONFIG_OF_BOARD_FIXUP
987 INIT_FUNC_WATCHDOG_RESET
992 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
997 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
998 !CONFIG_IS_ENABLED(X86_64)
1004 void board_init_f(ulong boot_flags)
1006 gd->flags = boot_flags;
1007 gd->have_console = 0;
1009 if (initcall_run_list(init_sequence_f))
1012 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
1013 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \
1014 !defined(CONFIG_ARC)
1015 /* NOTREACHED - jump_to_copy() does not return */
1020 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
1022 * For now this code is only used on x86.
1024 * init_sequence_f_r is the list of init functions which are run when
1025 * U-Boot is executing from Flash with a semi-limited 'C' environment.
1026 * The following limitations must be considered when implementing an
1028 * - 'static' variables are read-only
1029 * - Global Data (gd->xxx) is read/write
1031 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
1032 * supported). It _should_, if possible, copy global data to RAM and
1033 * initialise the CPU caches (to speed up the relocation process)
1035 * NOTE: At present only x86 uses this route, but it is intended that
1036 * all archs will move to this when generic relocation is implemented.
1038 static const init_fnc_t init_sequence_f_r[] = {
1039 #if !CONFIG_IS_ENABLED(X86_64)
1046 void board_init_f_r(void)
1048 if (initcall_run_list(init_sequence_f_r))
1052 * The pre-relocation drivers may be using memory that has now gone
1053 * away. Mark serial as unavailable - this will fall back to the debug
1054 * UART if available.
1056 * Do the same with log drivers since the memory may not be available.
1058 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY);
1064 * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
1065 * Transfer execution from Flash to RAM by calculating the address
1066 * of the in-RAM copy of board_init_r() and calling it
1068 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
1070 /* NOTREACHED - board_init_r() does not return */
1073 #endif /* CONFIG_X86 */