1 // SPDX-License-Identifier: GPL-2.0+
4 * Gerald Kerma <dreagle@doukki.net>
5 * Tony Dinh <mibodhi@gmail.com>
10 #include <asm/arch/cpu.h>
11 #include <asm/arch/soc.h>
12 #include <asm/arch/mpp.h>
16 DECLARE_GLOBAL_DATA_PTR;
18 int board_early_init_f(void)
21 * default gpio configuration
22 * There are maximum 64 gpios controlled through 2 sets of registers
23 * the below configuration configures mainly initial LED status
25 mvebu_config_gpio(NSA310S_VAL_LOW, NSA310S_VAL_HIGH,
26 NSA310S_OE_LOW, NSA310S_OE_HIGH);
28 /* (all LEDs & power off active high) */
29 /* Multi-Purpose Pins Functionality configuration */
30 static const u32 kwmpp_config[] = {
69 kirkwood_mpp_conf(kwmpp_config, NULL);
75 /* address of boot parameters */
76 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
81 #ifdef CONFIG_RESET_PHY_R
86 char *name = "egiga0";
88 if (miiphy_set_current_dev(name))
91 /* read PHY dev address */
92 if (miiphy_read(name, 0xee, 0xee, (u16 *) &phyaddr)) {
93 printf("could not read PHY dev address\n");
98 miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);
99 miiphy_read(name, phyaddr, MV88E1318_MAC_CTRL_REG, ®);
100 reg |= (MV88E1318_RGMII_RX_CTRL | MV88E1318_RGMII_TX_CTRL);
101 miiphy_write(name, phyaddr, MV88E1318_MAC_CTRL_REG, reg);
102 miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
105 if (miiphy_reset(name, phyaddr))
109 * ZyXEL NSA310S uses the 88E1310S Alaska (interface identical to 88E1318)
110 * and has an MCU attached to the LED[2] via tristate interrupt
113 /* switch to LED register page */
114 miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_LED_PG);
115 /* read out LED polarity register */
116 miiphy_read(name, phyaddr, MV88E1318_LED_POL_REG, ®);
117 /* clear 4, set 5 - LED2 low, tri-state */
118 reg &= ~(MV88E1318_LED2_4);
119 reg |= (MV88E1318_LED2_5);
120 /* write back LED polarity register */
121 miiphy_write(name, phyaddr, MV88E1318_LED_POL_REG, reg);
122 /* jump back to page 0, per the PHY chip documenation. */
123 miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
125 /* set PHY back to auto-negotiation mode */
126 miiphy_write(name, phyaddr, 0x4, 0x1e1);
127 miiphy_write(name, phyaddr, 0x9, 0x300);
129 miiphy_write(name, phyaddr, 0x10, 0x3860);
130 miiphy_write(name, phyaddr, 0x0, 0x9140);
132 #endif /* CONFIG_RESET_PHY_R */