2 * (C) Copyright 2006 DENX Software Engineering
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #if defined(CONFIG_CMD_NAND)
26 #ifdef CONFIG_NEW_NAND_CODE
29 #include <asm/arch/pxa-regs.h>
32 # define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
34 # define DFC_DEBUG1(fmt, args...)
38 # define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
40 # define DFC_DEBUG2(fmt, args...)
44 # define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
46 # define DFC_DEBUG3(fmt, args...)
49 #define MIN(x, y) ((x < y) ? x : y)
51 /* These really don't belong here, as they are specific to the NAND Model */
52 static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
54 static struct nand_bbt_descr delta_bbt_descr = {
58 .pattern = scan_ff_pattern
61 static struct nand_oobinfo delta_oob = {
62 .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */
64 .eccpos = {2, 3, 4, 5, 6, 7},
65 .oobfree = { {8, 2}, {12, 4} }
70 * not required for Monahans DFC
72 static void dfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
78 /* read device ready pin */
79 static int dfc_device_ready(struct mtd_info *mtdinfo)
90 * Write buf to the DFC Controller Data Buffer
92 static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
94 unsigned long bytes_multi = len & 0xfffffffc;
95 unsigned long rest = len & 0x3;
96 unsigned long *long_buf;
99 DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf));
101 for(i=0; i<bytes_multi; i+=4) {
102 long_buf = (unsigned long*) &buf[i];
107 printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n");
114 * static void dfc_read_buf(struct mtd_info *mtd, const u_char *buf, int len)
116 * Shouldn't this be "u_char * const buf" ?
118 static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
122 /* we have to be carefull not to overflow the buffer if len is
123 * not a multiple of 4 */
124 unsigned long bytes_multi = len & 0xfffffffc;
125 unsigned long rest = len & 0x3;
126 unsigned long *long_buf;
128 DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len);
129 /* if there are any, first copy multiple of 4 bytes */
131 for(i=0; i<bytes_multi; i+=4) {
132 long_buf = (unsigned long*) &buf[i];
137 /* ...then the rest */
139 unsigned long rest_data = NDDB;
141 buf[i+j] = (u_char) ((rest_data>>j) & 0xff);
148 * read a word. Not implemented as not used in NAND code.
150 static u16 dfc_read_word(struct mtd_info *mtd)
152 printf("dfc_read_word: UNIMPLEMENTED.\n");
156 /* global var, too bad: mk@tbd: move to ->priv pointer */
157 static unsigned long read_buf = 0;
158 static int bytes_read = -1;
161 * read a byte from NDDB Because we can only read 4 bytes from NDDB at
162 * a time, we buffer the remaining bytes. The buffer is reset when a
163 * new command is sent to the chip.
166 * This function is currently only used to read status and id
167 * bytes. For these commands always 8 bytes need to be read from
168 * NDDB. So we read and discard these bytes right now. In case this
169 * function is used for anything else in the future, we must check
170 * what was the last command issued and read the appropriate amount of
171 * bytes respectively.
173 static u_char dfc_read_byte(struct mtd_info *mtd)
183 byte = (unsigned char) (read_buf>>(8 * bytes_read++));
187 DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf);
191 /* calculate delta between OSCR values start and now */
192 static unsigned long get_delta(unsigned long start)
194 unsigned long cur = OSCR;
196 if(cur < start) /* OSCR overflowed */
197 return (cur + (start^0xffffffff));
199 return (cur - start);
202 /* delay function, this doesn't belong here */
203 static void wait_us(unsigned long us)
205 unsigned long start = OSCR;
208 while (get_delta(start) < us) {
213 static void dfc_clear_nddb(void)
215 NDCR &= ~NDCR_ND_RUN;
216 wait_us(CFG_NAND_OTHER_TO);
219 /* wait_event with timeout */
220 static unsigned long dfc_wait_event(unsigned long event)
222 unsigned long ndsr, timeout, start = OSCR;
226 else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
227 timeout = CFG_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ;
229 timeout = CFG_NAND_OTHER_TO * OSCR_CLK_FREQ;
237 if(get_delta(start) > timeout) {
238 DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%lx.\n", event);
246 /* we don't always wan't to do this */
247 static void dfc_new_cmd(void)
250 unsigned long status;
252 while(retry++ <= CFG_NAND_SENDCMD_RETRY) {
256 /* set NDCR[NDRUN] */
257 if(!(NDCR & NDCR_ND_RUN))
260 status = dfc_wait_event(NDSR_WRCMDREQ);
262 if(status & NDSR_WRCMDREQ)
265 DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry);
268 DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry);
271 /* this function is called after Programm and Erase Operations to
272 * check for success or failure */
273 static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this)
275 unsigned long ndsr=0, event=0;
276 int state = this->state;
278 if(state == FL_WRITING) {
279 event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
280 } else if(state == FL_ERASING) {
281 event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
284 ndsr = dfc_wait_event(event);
286 if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000))
287 return(0x1); /* Status Read error */
291 /* cmdfunc send commands to the DFC */
292 static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
293 int column, int page_addr)
295 /* register struct nand_chip *this = mtd->priv; */
296 unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0;
298 /* clear the ugly byte read buffer */
304 DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
306 ndcb0 = (NAND_CMD_READ0 | (4<<16));
307 column >>= 1; /* adjust for 16 bit bus */
308 ndcb1 = (((column>>1) & 0xff) |
309 ((page_addr<<8) & 0xff00) |
310 ((page_addr<<8) & 0xff0000) |
311 ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
315 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n");
317 case NAND_CMD_READOOB:
318 DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n");
320 case NAND_CMD_READID:
322 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n");
323 ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/
326 case NAND_CMD_PAGEPROG:
327 /* sent as a multicommand in NAND_CMD_SEQIN */
328 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n");
330 case NAND_CMD_ERASE1:
331 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
333 ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16));
334 ndcb1 = (page_addr & 0x00ffffff);
336 case NAND_CMD_ERASE2:
337 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n");
340 /* send PAGE_PROG command(0x1080) */
342 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
343 ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
344 column >>= 1; /* adjust for 16 bit bus */
345 ndcb1 = (((column>>1) & 0xff) |
346 ((page_addr<<8) & 0xff00) |
347 ((page_addr<<8) & 0xff0000) |
348 ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
351 case NAND_CMD_STATUS:
352 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n");
354 ndcb0 = NAND_CMD_STATUS | (4<<21);
358 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n");
359 ndcb0 = NAND_CMD_RESET | (5<<21);
360 event = NDSR_CS0_CMDD;
363 printk("dfc_cmdfunc: error, unsupported command.\n");
373 dfc_wait_event(event);
378 static void dfc_gpio_init(void)
380 DFC_DEBUG2("Setting up DFC GPIO's.\n");
382 /* no idea what is done here, see zylonite.c */
385 DF_ALE_WE1 = 0x00000001;
386 DF_ALE_WE2 = 0x00000001;
387 DF_nCS0 = 0x00000001;
388 DF_nCS1 = 0x00000001;
396 DF_IO10 = 0x00000001;
398 DF_IO11 = 0x00000001;
400 DF_IO12 = 0x00000001;
402 DF_IO13 = 0x00000001;
404 DF_IO14 = 0x00000001;
406 DF_IO15 = 0x00000001;
416 * Board-specific NAND initialization. The following members of the
417 * argument are board-specific (per include/linux/mtd/nand_new.h):
418 * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
419 * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
420 * - cmd_ctrl: hardwarespecific function for accesing control-lines
421 * - dev_ready: hardwarespecific function for accesing device ready/busy line
422 * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
423 * only be provided if a hardware ECC is available
424 * - ecc.mode: mode of ecc, see defines
425 * - chip_delay: chip dependent delay for transfering data from array to
427 * - options: various chip options. They can partly be set to inform
428 * nand_scan about special functionality. See the defines for further
430 * Members with a "?" were not set in the merged testing-NAND branch,
431 * so they are not set here either.
433 int board_nand_init(struct nand_chip *nand)
435 unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
437 /* set up GPIO Control Registers */
440 /* turn on the NAND Controller Clock (104 MHz @ D0) */
441 CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
443 #undef CFG_TIMING_TIGHT
444 #ifndef CFG_TIMING_TIGHT
445 tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
447 tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
449 tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
451 tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
453 tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
455 tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
457 tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
459 tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
461 tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
463 #else /* this is the tight timing */
465 tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
467 tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
469 tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)),
471 tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)),
473 tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)),
475 tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)),
477 tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2),
479 tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2),
481 tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
483 #endif /* CFG_TIMING_TIGHT */
486 DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
488 /* tRP value is split in the register */
496 NDTR0CS0 = (tCH << 19) |
504 NDTR1CS0 = (tR << 16) |
508 /* If it doesn't work (unlikely) think about:
510 * - chip select don't care
511 * - read id byte count
513 * Intentionally enabled by not setting bits:
516 * - cs don't care, see if we can enable later!
517 * - row address start position (after second cycle)
518 * - pages per block = 32
519 * - ND_RDY : clears command buffer
521 /* NDCR_NCSX | /\* Chip select busy don't care *\/ */
523 NDCR = (NDCR_SPARE_EN | /* use the spare area */
524 NDCR_DWIDTH_C | /* 16bit DFC data bus width */
525 NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
526 (2 << 16) | /* read id count = 7 ???? mk@tbd */
527 NDCR_ND_ARB_EN | /* enable bus arbiter */
528 NDCR_RDYM | /* flash device ready ir masked */
529 NDCR_CS0_PAGEDM | /* ND_nCSx page done ir masked */
531 NDCR_CS0_CMDDM | /* ND_CSx command done ir masked */
533 NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */
535 NDCR_DBERRM | /* double bit error ir masked */
536 NDCR_SBERRM | /* single bit error ir masked */
537 NDCR_WRDREQM | /* write data request ir masked */
538 NDCR_RDDREQM | /* read data request ir masked */
539 NDCR_WRCMDREQM); /* write command request ir masked */
542 /* wait 10 us due to cmd buffer clear reset */
545 nand->cmd_ctrl = dfc_hwcontrol;
546 /* nand->dev_ready = dfc_device_ready; */
547 nand->ecc.mode = NAND_ECC_SOFT;
548 nand->options = NAND_BUSWIDTH_16;
549 nand->waitfunc = dfc_wait;
550 nand->read_byte = dfc_read_byte;
551 nand->read_word = dfc_read_word;
552 nand->read_buf = dfc_read_buf;
553 nand->write_buf = dfc_write_buf;
555 nand->cmdfunc = dfc_cmdfunc;
556 /* nand->autooob = &delta_oob; */
557 nand->badblock_pattern = &delta_bbt_descr;
562 #error "U-Boot legacy NAND support not available for Monahans DFC."