2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/clk.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/sys_proto.h>
18 #include <dwc3-uboot.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
26 !defined(CONFIG_SPL_BUILD)
27 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
32 } zynqmp_devices[] = {
79 static int chip_id(void)
82 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
91 * regs[0][31:0] = status of the operation
92 * regs[0][63:32] = CSU.IDCODE register
93 * regs[1][31:0] = CSU.version register
95 regs.regs[0] = upper_32_bits(regs.regs[0]);
96 regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
97 ZYNQMP_CSU_IDCODE_SVD_MASK;
98 regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
103 static char *zynqmp_get_silicon_idcode_name(void)
108 for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
109 if (zynqmp_devices[i].id == id)
110 return zynqmp_devices[i].name;
116 #define ZYNQMP_VERSION_SIZE 9
120 printf("EL Level:\tEL%d\n", current_el());
122 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
123 !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
124 defined(CONFIG_SPL_BUILD))
125 if (current_el() != 3) {
126 static char version[ZYNQMP_VERSION_SIZE];
128 strncat(version, "xczu", ZYNQMP_VERSION_SIZE);
129 zynqmppl.name = strncat(version,
130 zynqmp_get_silicon_idcode_name(),
131 ZYNQMP_VERSION_SIZE);
132 printf("Chip ID:\t%s\n", zynqmppl.name);
134 fpga_add(fpga_xilinx, &zynqmppl);
141 int board_early_init_r(void)
145 if (current_el() == 3) {
146 val = readl(&crlapb_base->timestamp_ref_ctrl);
147 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
148 writel(val, &crlapb_base->timestamp_ref_ctrl);
150 /* Program freq register in System counter */
151 writel(zynqmp_get_system_timer_freq(),
152 &iou_scntr_secure->base_frequency_id_register);
153 /* And enable system counter */
154 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
155 &iou_scntr_secure->counter_control_register);
157 /* Program freq register in System counter and enable system counter */
158 writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
159 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
160 ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
161 &iou_scntr->counter_control_register);
166 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
168 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
169 defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
170 defined(CONFIG_ZYNQ_EEPROM_BUS)
171 i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
173 if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
174 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
176 printf("I2C EEPROM MAC address read failed\n");
182 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
183 void dram_init_banksize(void)
185 fdtdec_setup_memory_banksize();
190 if (fdtdec_setup_memory_size() != 0)
198 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
204 void reset_cpu(ulong addr)
208 int board_late_init(void)
215 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
216 debug("Saved variables - Skipping\n");
220 reg = readl(&crlapb_base->boot_mode);
221 if (reg >> BOOT_MODE_ALT_SHIFT)
222 reg >>= BOOT_MODE_ALT_SHIFT;
224 bootmode = reg & BOOT_MODES_MASK;
236 case QSPI_MODE_24BIT:
237 case QSPI_MODE_32BIT:
254 #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
266 printf("Invalid Boot Mode:0x%x\n", bootmode);
271 * One terminating char + one byte for space between mode
272 * and default boot_targets
274 new_targets = calloc(1, strlen(mode) +
275 strlen(getenv("boot_targets")) + 2);
277 sprintf(new_targets, "%s %s", mode, getenv("boot_targets"));
278 setenv("boot_targets", new_targets);
285 puts("Board: Xilinx ZynqMP\n");
289 #ifdef CONFIG_USB_DWC3
290 static struct dwc3_device dwc3_device_data0 = {
291 .maximum_speed = USB_SPEED_HIGH,
292 .base = ZYNQMP_USB0_XHCI_BASEADDR,
293 .dr_mode = USB_DR_MODE_PERIPHERAL,
297 static struct dwc3_device dwc3_device_data1 = {
298 .maximum_speed = USB_SPEED_HIGH,
299 .base = ZYNQMP_USB1_XHCI_BASEADDR,
300 .dr_mode = USB_DR_MODE_PERIPHERAL,
304 int usb_gadget_handle_interrupts(int index)
306 dwc3_uboot_handle_interrupt(index);
310 int board_usb_init(int index, enum usb_init_type init)
312 debug("%s: index %x\n", __func__, index);
314 #if defined(CONFIG_USB_GADGET_DOWNLOAD)
315 g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
320 return dwc3_uboot_init(&dwc3_device_data0);
322 return dwc3_uboot_init(&dwc3_device_data1);
328 int board_usb_cleanup(int index, enum usb_init_type init)
330 dwc3_uboot_exit(index);