2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/hardware.h>
13 #include <asm/arch/sys_proto.h>
16 #include <dwc3-uboot.h>
18 DECLARE_GLOBAL_DATA_PTR;
22 printf("EL Level:\tEL%d\n", current_el());
27 int board_early_init_r(void)
31 val = readl(&crlapb_base->timestamp_ref_ctrl);
32 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
33 writel(val, &crlapb_base->timestamp_ref_ctrl);
35 /* Program freq register in System counter and enable system counter */
36 writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
37 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
38 ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
39 &iou_scntr->counter_control_register);
46 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
56 void reset_cpu(ulong addr)
60 #ifdef CONFIG_SCSI_AHCI_PLAT
63 ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
68 int board_eth_init(bd_t *bis)
72 #if defined(CONFIG_ZYNQ_GEM)
73 # if defined(CONFIG_ZYNQ_GEM0)
74 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
75 CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
77 # if defined(CONFIG_ZYNQ_GEM1)
78 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
79 CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
81 # if defined(CONFIG_ZYNQ_GEM2)
82 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR2,
83 CONFIG_ZYNQ_GEM_PHY_ADDR2, 0);
85 # if defined(CONFIG_ZYNQ_GEM3)
86 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR3,
87 CONFIG_ZYNQ_GEM_PHY_ADDR3, 0);
94 int board_mmc_init(bd_t *bd)
98 u32 ver = zynqmp_get_silicon_version();
100 if (ver != ZYNQMP_CSU_VERSION_VELOCE) {
101 #if defined(CONFIG_ZYNQ_SDHCI)
102 # if defined(CONFIG_ZYNQ_SDHCI0)
103 ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
105 # if defined(CONFIG_ZYNQ_SDHCI1)
106 ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
115 int board_late_init(void)
120 reg = readl(&crlapb_base->boot_mode);
121 bootmode = reg & BOOT_MODES_MASK;
126 setenv("modeboot", "sdboot");
129 printf("Invalid Boot Mode:0x%x\n", bootmode);
138 puts("Board:\tXilinx ZynqMP\n");
142 #ifdef CONFIG_USB_DWC3
143 static struct dwc3_device dwc3_device_data = {
144 .maximum_speed = USB_SPEED_HIGH,
145 .base = ZYNQMP_USB0_XHCI_BASEADDR,
146 .dr_mode = USB_DR_MODE_PERIPHERAL,
150 int usb_gadget_handle_interrupts(void)
152 dwc3_uboot_handle_interrupt(0);
156 int board_usb_init(int index, enum usb_init_type init)
158 return dwc3_uboot_init(&dwc3_device_data);
161 int board_usb_cleanup(int index, enum usb_init_type init)
163 dwc3_uboot_exit(index);