1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
13 #include <asm/arch/clk.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/arch/psu_init_gpl.h>
18 #include <dm/device.h>
19 #include <dm/uclass.h>
21 #include <dwc3-uboot.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
29 static struct udevice *watchdog_dev;
32 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
33 !defined(CONFIG_SPL_BUILD)
34 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
41 } zynqmp_devices[] = {
130 { /* For testing purpose only */
174 int chip_id(unsigned char id)
179 if (current_el() != 3) {
180 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
189 * regs[0][31:0] = status of the operation
190 * regs[0][63:32] = CSU.IDCODE register
191 * regs[1][31:0] = CSU.version register
192 * regs[1][63:32] = CSU.IDCODE2 register
196 regs.regs[0] = upper_32_bits(regs.regs[0]);
197 regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
198 ZYNQMP_CSU_IDCODE_SVD_MASK;
199 regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
203 regs.regs[1] = lower_32_bits(regs.regs[1]);
204 regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
208 regs.regs[1] = lower_32_bits(regs.regs[1]);
209 regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
213 printf("%s, Invalid Req:0x%x\n", __func__, id);
218 val = readl(ZYNQMP_CSU_IDCODE_ADDR);
219 val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
220 ZYNQMP_CSU_IDCODE_SVD_MASK;
221 val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
224 val = readl(ZYNQMP_CSU_VER_ADDR);
225 val &= ZYNQMP_CSU_SILICON_VER_MASK;
228 printf("%s, Invalid Req:0x%x\n", __func__, id);
235 #define ZYNQMP_VERSION_SIZE 9
236 #define ZYNQMP_PL_STATUS_BIT 9
237 #define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
238 #define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
240 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
241 !defined(CONFIG_SPL_BUILD)
242 static char *zynqmp_get_silicon_idcode_name(void)
246 static char name[ZYNQMP_VERSION_SIZE];
248 id = chip_id(IDCODE);
249 ver = chip_id(IDCODE2);
251 for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
252 if ((zynqmp_devices[i].id == id) &&
253 (zynqmp_devices[i].ver == (ver &
254 ZYNQMP_CSU_VERSION_MASK))) {
255 strncat(name, "zu", 2);
256 strncat(name, zynqmp_devices[i].name,
257 ZYNQMP_VERSION_SIZE - 3);
262 if (i >= ARRAY_SIZE(zynqmp_devices))
265 if (!zynqmp_devices[i].evexists)
268 if (ver & ZYNQMP_PL_STATUS_MASK)
271 if (strstr(name, "eg") || strstr(name, "ev")) {
272 buf = strstr(name, "e");
280 int board_early_init_f(void)
283 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
284 zynqmp_pmufw_version();
287 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
291 #if defined(CONFIG_WDT) && !defined(CONFIG_SPL_BUILD)
292 /* bss is not cleared at time when watchdog_reset() is called */
301 printf("EL Level:\tEL%d\n", current_el());
303 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
304 !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
305 defined(CONFIG_SPL_BUILD))
306 if (current_el() != 3) {
307 zynqmppl.name = zynqmp_get_silicon_idcode_name();
308 printf("Chip ID:\t%s\n", zynqmppl.name);
310 fpga_add(fpga_xilinx, &zynqmppl);
314 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
315 if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) {
316 debug("Watchdog: Not found by seq!\n");
317 if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
318 puts("Watchdog: Not found!\n");
323 wdt_start(watchdog_dev, 0, 0);
324 puts("Watchdog: Started\n");
330 #ifdef CONFIG_WATCHDOG
331 /* Called by macro WATCHDOG_RESET */
332 void watchdog_reset(void)
334 # if !defined(CONFIG_SPL_BUILD)
335 static ulong next_reset;
341 now = timer_get_us();
343 /* Do not reset the watchdog too often */
344 if (now > next_reset) {
345 wdt_reset(watchdog_dev);
346 next_reset = now + 1000;
352 int board_early_init_r(void)
356 if (current_el() != 3)
359 val = readl(&crlapb_base->timestamp_ref_ctrl);
360 val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
363 val = readl(&crlapb_base->timestamp_ref_ctrl);
364 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
365 writel(val, &crlapb_base->timestamp_ref_ctrl);
367 /* Program freq register in System counter */
368 writel(zynqmp_get_system_timer_freq(),
369 &iou_scntr_secure->base_frequency_id_register);
370 /* And enable system counter */
371 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
372 &iou_scntr_secure->counter_control_register);
377 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
379 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
380 defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
381 defined(CONFIG_ZYNQ_EEPROM_BUS)
382 i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
384 if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
385 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
387 printf("I2C EEPROM MAC address read failed\n");
393 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
398 if (current_el() > 1) {
401 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
404 printf("FAIL: current EL is not above EL1\n");
410 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
411 int dram_init_banksize(void)
415 ret = fdtdec_setup_memory_banksize();
426 if (fdtdec_setup_mem_size_base() != 0)
432 int dram_init_banksize(void)
434 #if defined(CONFIG_NR_DRAM_BANKS)
435 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
436 gd->bd->bi_dram[0].size = get_effective_memsize();
446 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
447 CONFIG_SYS_SDRAM_SIZE);
453 void reset_cpu(ulong addr)
457 static const struct {
460 } reset_reasons[] = {
461 { RESET_REASON_DEBUG_SYS, "DEBUG" },
462 { RESET_REASON_SOFT, "SOFT" },
463 { RESET_REASON_SRST, "SRST" },
464 { RESET_REASON_PSONLY, "PS-ONLY" },
465 { RESET_REASON_PMU, "PMU" },
466 { RESET_REASON_INTERNAL, "INTERNAL" },
467 { RESET_REASON_EXTERNAL, "EXTERNAL" },
471 static u32 reset_reason(void)
475 const char *reason = NULL;
477 ret = readl(&crlapb_base->reset_reason);
479 puts("Reset reason:\t");
481 for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
482 if (ret & reset_reasons[i].bit) {
483 reason = reset_reasons[i].name;
484 printf("%s ", reset_reasons[i].name);
491 env_set("reset_reason", reason);
493 writel(~0, &crlapb_base->reset_reason);
498 int board_late_init(void)
505 int env_targets_len = 0;
511 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
512 debug("Saved variables - Skipping\n");
516 ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®);
520 if (reg >> BOOT_MODE_ALT_SHIFT)
521 reg >>= BOOT_MODE_ALT_SHIFT;
523 bootmode = reg & BOOT_MODES_MASK;
530 env_set("modeboot", "usb_dfu_spl");
535 env_set("modeboot", "jtagboot");
537 case QSPI_MODE_24BIT:
538 case QSPI_MODE_32BIT:
541 env_set("modeboot", "qspiboot");
546 env_set("modeboot", "emmcboot");
550 if (uclass_get_device_by_name(UCLASS_MMC,
551 "sdhci@ff160000", &dev)) {
552 puts("Boot from SD0 but without SD0 enabled!\n");
555 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
559 env_set("modeboot", "sdboot");
566 if (uclass_get_device_by_name(UCLASS_MMC,
567 "sdhci@ff170000", &dev)) {
568 puts("Boot from SD1 but without SD1 enabled!\n");
571 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
575 env_set("modeboot", "sdboot");
580 env_set("modeboot", "nandboot");
584 printf("Invalid Boot Mode:0x%x\n", bootmode);
589 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
590 debug("Bootseq len: %x\n", bootseq_len);
594 * One terminating char + one byte for space between mode
595 * and default boot_targets
597 env_targets = env_get("boot_targets");
599 env_targets_len = strlen(env_targets);
601 new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
607 sprintf(new_targets, "%s%x %s", mode, bootseq,
608 env_targets ? env_targets : "");
610 sprintf(new_targets, "%s %s", mode,
611 env_targets ? env_targets : "");
613 env_set("boot_targets", new_targets);
622 puts("Board: Xilinx ZynqMP\n");