1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
9 #include <debug_uart.h>
17 #include <asm/arch/clk.h>
18 #include <asm/arch/hardware.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/arch/psu_init_gpl.h>
22 #include <dm/device.h>
23 #include <dm/uclass.h>
25 #include <dwc3-uboot.h>
27 #include <zynqmp_firmware.h>
29 #include <linux/sizes.h>
31 #include "pm_cfg_obj.h"
33 DECLARE_GLOBAL_DATA_PTR;
35 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
36 !defined(CONFIG_SPL_BUILD)
37 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
44 } zynqmp_devices[] = {
136 { /* For testing purpose only */
192 int chip_id(unsigned char id)
197 if (current_el() != 3) {
198 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
207 * regs[0][31:0] = status of the operation
208 * regs[0][63:32] = CSU.IDCODE register
209 * regs[1][31:0] = CSU.version register
210 * regs[1][63:32] = CSU.IDCODE2 register
214 regs.regs[0] = upper_32_bits(regs.regs[0]);
215 regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
216 ZYNQMP_CSU_IDCODE_SVD_MASK;
217 regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
221 regs.regs[1] = lower_32_bits(regs.regs[1]);
222 regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
226 regs.regs[1] = lower_32_bits(regs.regs[1]);
227 regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
231 printf("%s, Invalid Req:0x%x\n", __func__, id);
236 val = readl(ZYNQMP_CSU_IDCODE_ADDR);
237 val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
238 ZYNQMP_CSU_IDCODE_SVD_MASK;
239 val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
242 val = readl(ZYNQMP_CSU_VER_ADDR);
243 val &= ZYNQMP_CSU_SILICON_VER_MASK;
246 printf("%s, Invalid Req:0x%x\n", __func__, id);
253 #define ZYNQMP_VERSION_SIZE 9
254 #define ZYNQMP_PL_STATUS_BIT 9
255 #define ZYNQMP_IPDIS_VCU_BIT 8
256 #define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
257 #define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
258 #define ZYNQMP_CSU_VCUDIS_VER_MASK ZYNQMP_CSU_VERSION_MASK & \
259 ~BIT(ZYNQMP_IPDIS_VCU_BIT)
260 #define MAX_VARIANTS_EV 3
262 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
263 !defined(CONFIG_SPL_BUILD)
264 static char *zynqmp_get_silicon_idcode_name(void)
268 static char name[ZYNQMP_VERSION_SIZE];
270 id = chip_id(IDCODE);
271 ver = chip_id(IDCODE2);
273 for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
274 if (zynqmp_devices[i].id == id) {
275 if (zynqmp_devices[i].evexists &&
276 !(ver & ZYNQMP_PL_STATUS_MASK))
278 if (zynqmp_devices[i].ver == (ver &
279 ZYNQMP_CSU_VERSION_MASK))
284 if (i >= ARRAY_SIZE(zynqmp_devices))
287 strncat(name, "zu", 2);
288 if (!zynqmp_devices[i].evexists ||
289 (ver & ZYNQMP_PL_STATUS_MASK)) {
290 strncat(name, zynqmp_devices[i].name,
291 ZYNQMP_VERSION_SIZE - 3);
296 * Here we are means, PL not powered up and ev variant
297 * exists. So, we need to ignore VCU disable bit(8) in
298 * version and findout if its CG or EG/EV variant.
300 for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
301 if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
302 (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
303 strncat(name, zynqmp_devices[i].name,
304 ZYNQMP_VERSION_SIZE - 3);
309 if (j >= MAX_VARIANTS_EV)
312 if (strstr(name, "eg") || strstr(name, "ev")) {
313 buf = strstr(name, "e");
321 int board_early_init_f(void)
323 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
330 /* Delay is required for clocks to be propagated */
334 #ifdef CONFIG_DEBUG_UART
335 /* Uart debug for sure */
337 puts("Debug uart enabled\n"); /* or printch() */
343 static int multi_boot(void)
347 multiboot = readl(&csu_base->multi_boot);
349 printf("Multiboot:\t%x\n", multiboot);
356 #if defined(CONFIG_ZYNQMP_FIRMWARE)
359 uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
361 panic("PMU Firmware device not found - Enable it");
364 #if defined(CONFIG_SPL_BUILD)
365 /* Check *at build time* if the filename is an non-empty string */
366 if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
367 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
368 zynqmp_pm_cfg_obj_size);
371 printf("EL Level:\tEL%d\n", current_el());
373 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
374 !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
375 defined(CONFIG_SPL_BUILD))
376 if (current_el() != 3) {
377 zynqmppl.name = zynqmp_get_silicon_idcode_name();
378 printf("Chip ID:\t%s\n", zynqmppl.name);
380 fpga_add(fpga_xilinx, &zynqmppl);
384 if (current_el() == 3)
390 int board_early_init_r(void)
394 if (current_el() != 3)
397 val = readl(&crlapb_base->timestamp_ref_ctrl);
398 val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
401 val = readl(&crlapb_base->timestamp_ref_ctrl);
402 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
403 writel(val, &crlapb_base->timestamp_ref_ctrl);
405 /* Program freq register in System counter */
406 writel(zynqmp_get_system_timer_freq(),
407 &iou_scntr_secure->base_frequency_id_register);
408 /* And enable system counter */
409 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
410 &iou_scntr_secure->counter_control_register);
415 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
420 if (current_el() > 1) {
423 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
426 printf("FAIL: current EL is not above EL1\n");
432 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
433 int dram_init_banksize(void)
437 ret = fdtdec_setup_memory_banksize();
448 if (fdtdec_setup_mem_size_base() != 0)
454 int dram_init_banksize(void)
456 #if defined(CONFIG_NR_DRAM_BANKS)
457 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
458 gd->bd->bi_dram[0].size = get_effective_memsize();
468 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
469 CONFIG_SYS_SDRAM_SIZE);
475 void reset_cpu(ulong addr)
479 #if defined(CONFIG_BOARD_LATE_INIT)
480 static const struct {
483 } reset_reasons[] = {
484 { RESET_REASON_DEBUG_SYS, "DEBUG" },
485 { RESET_REASON_SOFT, "SOFT" },
486 { RESET_REASON_SRST, "SRST" },
487 { RESET_REASON_PSONLY, "PS-ONLY" },
488 { RESET_REASON_PMU, "PMU" },
489 { RESET_REASON_INTERNAL, "INTERNAL" },
490 { RESET_REASON_EXTERNAL, "EXTERNAL" },
494 static int reset_reason(void)
498 const char *reason = NULL;
500 ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, ®);
504 puts("Reset reason:\t");
506 for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
507 if (reg & reset_reasons[i].bit) {
508 reason = reset_reasons[i].name;
509 printf("%s ", reset_reasons[i].name);
516 env_set("reset_reason", reason);
518 ret = zynqmp_mmio_write(~0, ~0, (ulong)&crlapb_base->reset_reason);
525 static int set_fdtfile(void)
527 char *compatible, *fdtfile;
528 const char *suffix = ".dtb";
529 const char *vendor = "xilinx/";
531 if (env_get("fdtfile"))
534 compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
536 debug("Compatible: %s\n", compatible);
538 /* Discard vendor prefix */
539 strsep(&compatible, ",");
541 fdtfile = calloc(1, strlen(vendor) + strlen(compatible) +
546 sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix);
548 env_set("fdtfile", fdtfile);
555 int board_late_init(void)
562 int env_targets_len = 0;
569 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
573 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
574 debug("Saved variables - Skipping\n");
582 ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®);
586 if (reg >> BOOT_MODE_ALT_SHIFT)
587 reg >>= BOOT_MODE_ALT_SHIFT;
589 bootmode = reg & BOOT_MODES_MASK;
596 env_set("modeboot", "usb_dfu_spl");
600 mode = "jtag pxe dhcp";
601 env_set("modeboot", "jtagboot");
603 case QSPI_MODE_24BIT:
604 case QSPI_MODE_32BIT:
607 env_set("modeboot", "qspiboot");
611 if (uclass_get_device_by_name(UCLASS_MMC,
612 "mmc@ff160000", &dev) &&
613 uclass_get_device_by_name(UCLASS_MMC,
614 "sdhci@ff160000", &dev)) {
615 puts("Boot from EMMC but without SD0 enabled!\n");
618 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
625 if (uclass_get_device_by_name(UCLASS_MMC,
626 "mmc@ff160000", &dev) &&
627 uclass_get_device_by_name(UCLASS_MMC,
628 "sdhci@ff160000", &dev)) {
629 puts("Boot from SD0 but without SD0 enabled!\n");
632 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
636 env_set("modeboot", "sdboot");
643 if (uclass_get_device_by_name(UCLASS_MMC,
644 "mmc@ff170000", &dev) &&
645 uclass_get_device_by_name(UCLASS_MMC,
646 "sdhci@ff170000", &dev)) {
647 puts("Boot from SD1 but without SD1 enabled!\n");
650 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
654 env_set("modeboot", "sdboot");
659 env_set("modeboot", "nandboot");
663 printf("Invalid Boot Mode:0x%x\n", bootmode);
668 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
669 debug("Bootseq len: %x\n", bootseq_len);
673 * One terminating char + one byte for space between mode
674 * and default boot_targets
676 env_targets = env_get("boot_targets");
678 env_targets_len = strlen(env_targets);
680 new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
686 sprintf(new_targets, "%s%x %s", mode, bootseq,
687 env_targets ? env_targets : "");
689 sprintf(new_targets, "%s %s", mode,
690 env_targets ? env_targets : "");
692 env_set("boot_targets", new_targets);
694 initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
695 initrd_hi = round_down(initrd_hi, SZ_16M);
696 env_set_addr("initrd_high", (void *)initrd_hi);
698 env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
708 puts("Board: Xilinx ZynqMP\n");