board/xilinx/zynqmp/zynqmp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <env.h>
  10 #include <init.h>
  11 #include <sata.h>
  12 #include <ahci.h>
  13 #include <scsi.h>
  14 #include <malloc.h>
  15 #include <wdt.h>
  16 #include <asm/arch/clk.h>
  17 #include <asm/arch/hardware.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/arch/psu_init_gpl.h>
  20 #include <asm/io.h>
  21 #include <dm/device.h>
  22 #include <dm/uclass.h>
  23 #include <usb.h>
  24 #include <dwc3-uboot.h>
  25 #include <zynqmppl.h>
  26 #include <zynqmp_firmware.h>
  27 #include <g_dnl.h>
  28 #include <linux/sizes.h>
  29
  30 #include "pm_cfg_obj.h"
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  35     !defined(CONFIG_SPL_BUILD)
  36 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  37
  38 static const struct {
  39         u32 id;
  40         u32 ver;
  41         char *name;
  42         bool evexists;
  43 } zynqmp_devices[] = {
  44         {
  45                 .id = 0x10,
  46                 .name = "3eg",
  47         },
  48         {
  49                 .id = 0x10,
  50                 .ver = 0x2c,
  51                 .name = "3cg",
  52         },
  53         {
  54                 .id = 0x11,
  55                 .name = "2eg",
  56         },
  57         {
  58                 .id = 0x11,
  59                 .ver = 0x2c,
  60                 .name = "2cg",
  61         },
  62         {
  63                 .id = 0x20,
  64                 .name = "5ev",
  65                 .evexists = 1,
  66         },
  67         {
  68                 .id = 0x20,
  69                 .ver = 0x100,
  70                 .name = "5eg",
  71                 .evexists = 1,
  72         },
  73         {
  74                 .id = 0x20,
  75                 .ver = 0x12c,
  76                 .name = "5cg",
  77                 .evexists = 1,
  78         },
  79         {
  80                 .id = 0x21,
  81                 .name = "4ev",
  82                 .evexists = 1,
  83         },
  84         {
  85                 .id = 0x21,
  86                 .ver = 0x100,
  87                 .name = "4eg",
  88                 .evexists = 1,
  89         },
  90         {
  91                 .id = 0x21,
  92                 .ver = 0x12c,
  93                 .name = "4cg",
  94                 .evexists = 1,
  95         },
  96         {
  97                 .id = 0x30,
  98                 .name = "7ev",
  99                 .evexists = 1,
 100         },
 101         {
 102                 .id = 0x30,
 103                 .ver = 0x100,
 104                 .name = "7eg",
 105                 .evexists = 1,
 106         },
 107         {
 108                 .id = 0x30,
 109                 .ver = 0x12c,
 110                 .name = "7cg",
 111                 .evexists = 1,
 112         },
 113         {
 114                 .id = 0x38,
 115                 .name = "9eg",
 116         },
 117         {
 118                 .id = 0x38,
 119                 .ver = 0x2c,
 120                 .name = "9cg",
 121         },
 122         {
 123                 .id = 0x39,
 124                 .name = "6eg",
 125         },
 126         {
 127                 .id = 0x39,
 128                 .ver = 0x2c,
 129                 .name = "6cg",
 130         },
 131         {
 132                 .id = 0x40,
 133                 .name = "11eg",
 134         },
 135         { /* For testing purpose only */
 136                 .id = 0x50,
 137                 .ver = 0x2c,
 138                 .name = "15cg",
 139         },
 140         {
 141                 .id = 0x50,
 142                 .name = "15eg",
 143         },
 144         {
 145                 .id = 0x58,
 146                 .name = "19eg",
 147         },
 148         {
 149                 .id = 0x59,
 150                 .name = "17eg",
 151         },
 152         {
 153                 .id = 0x61,
 154                 .name = "21dr",
 155         },
 156         {
 157                 .id = 0x63,
 158                 .name = "23dr",
 159         },
 160         {
 161                 .id = 0x65,
 162                 .name = "25dr",
 163         },
 164         {
 165                 .id = 0x64,
 166                 .name = "27dr",
 167         },
 168         {
 169                 .id = 0x60,
 170                 .name = "28dr",
 171         },
 172         {
 173                 .id = 0x62,
 174                 .name = "29dr",
 175         },
 176         {
 177                 .id = 0x66,
 178                 .name = "39dr",
 179         },
 180         {
 181                 .id = 0x7b,
 182                 .name = "48dr",
 183         },
 184         {
 185                 .id = 0x7e,
 186                 .name = "49dr",
 187         },
 188 };
 189 #endif
 190
 191 int chip_id(unsigned char id)
 192 {
 193         struct pt_regs regs;
 194         int val = -EINVAL;
 195
 196         if (current_el() != 3) {
 197                 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
 198                 regs.regs[1] = 0;
 199                 regs.regs[2] = 0;
 200                 regs.regs[3] = 0;
 201
 202                 smc_call(&regs);
 203
 204                 /*
 205                  * SMC returns:
 206                  * regs[0][31:0]  = status of the operation
 207                  * regs[0][63:32] = CSU.IDCODE register
 208                  * regs[1][31:0]  = CSU.version register
 209                  * regs[1][63:32] = CSU.IDCODE2 register
 210                  */
 211                 switch (id) {
 212                 case IDCODE:
 213                         regs.regs[0] = upper_32_bits(regs.regs[0]);
 214                         regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 215                                         ZYNQMP_CSU_IDCODE_SVD_MASK;
 216                         regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 217                         val = regs.regs[0];
 218                         break;
 219                 case VERSION:
 220                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 221                         regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
 222                         val = regs.regs[1];
 223                         break;
 224                 case IDCODE2:
 225                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 226                         regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
 227                         val = regs.regs[1];
 228                         break;
 229                 default:
 230                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 231                 }
 232         } else {
 233                 switch (id) {
 234                 case IDCODE:
 235                         val = readl(ZYNQMP_CSU_IDCODE_ADDR);
 236                         val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 237                                ZYNQMP_CSU_IDCODE_SVD_MASK;
 238                         val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 239                         break;
 240                 case VERSION:
 241                         val = readl(ZYNQMP_CSU_VER_ADDR);
 242                         val &= ZYNQMP_CSU_SILICON_VER_MASK;
 243                         break;
 244                 default:
 245                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 246                 }
 247         }
 248
 249         return val;
 250 }
 251
 252 #define ZYNQMP_VERSION_SIZE             9
 253 #define ZYNQMP_PL_STATUS_BIT            9
 254 #define ZYNQMP_IPDIS_VCU_BIT            8
 255 #define ZYNQMP_PL_STATUS_MASK           BIT(ZYNQMP_PL_STATUS_BIT)
 256 #define ZYNQMP_CSU_VERSION_MASK         ~(ZYNQMP_PL_STATUS_MASK)
 257 #define ZYNQMP_CSU_VCUDIS_VER_MASK      ZYNQMP_CSU_VERSION_MASK & \
 258                                         ~BIT(ZYNQMP_IPDIS_VCU_BIT)
 259 #define MAX_VARIANTS_EV                 3
 260
 261 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 262         !defined(CONFIG_SPL_BUILD)
 263 static char *zynqmp_get_silicon_idcode_name(void)
 264 {
 265         u32 i, id, ver, j;
 266         char *buf;
 267         static char name[ZYNQMP_VERSION_SIZE];
 268
 269         id = chip_id(IDCODE);
 270         ver = chip_id(IDCODE2);
 271
 272         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 273                 if (zynqmp_devices[i].id == id) {
 274                         if (zynqmp_devices[i].evexists &&
 275                             !(ver & ZYNQMP_PL_STATUS_MASK))
 276                                 break;
 277                         if (zynqmp_devices[i].ver == (ver &
 278                             ZYNQMP_CSU_VERSION_MASK))
 279                                 break;
 280                 }
 281         }
 282
 283         if (i >= ARRAY_SIZE(zynqmp_devices))
 284                 return "unknown";
 285
 286         strncat(name, "zu", 2);
 287         if (!zynqmp_devices[i].evexists ||
 288             (ver & ZYNQMP_PL_STATUS_MASK)) {
 289                 strncat(name, zynqmp_devices[i].name,
 290                         ZYNQMP_VERSION_SIZE - 3);
 291                 return name;
 292         }
 293
 294         /*
 295          * Here we are means, PL not powered up and ev variant
 296          * exists. So, we need to ignore VCU disable bit(8) in
 297          * version and findout if its CG or EG/EV variant.
 298          */
 299         for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
 300                 if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
 301                     (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
 302                         strncat(name, zynqmp_devices[i].name,
 303                                 ZYNQMP_VERSION_SIZE - 3);
 304                         break;
 305                 }
 306         }
 307
 308         if (j >= MAX_VARIANTS_EV)
 309                 return "unknown";
 310
 311         if (strstr(name, "eg") || strstr(name, "ev")) {
 312                 buf = strstr(name, "e");
 313                 *buf = '\0';
 314         }
 315
 316         return name;
 317 }
 318 #endif
 319
 320 int board_early_init_f(void)
 321 {
 322         int ret = 0;
 323
 324 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 325         ret = psu_init();
 326 #endif
 327
 328         return ret;
 329 }
 330
 331 static int multi_boot(void)
 332 {
 333         u32 multiboot;
 334
 335         multiboot = readl(&csu_base->multi_boot);
 336
 337         printf("Multiboot:\t%x\n", multiboot);
 338
 339         return 0;
 340 }
 341
 342 int board_init(void)
 343 {
 344 #if defined(CONFIG_ZYNQMP_FIRMWARE)
 345         struct udevice *dev;
 346
 347         uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
 348         if (!dev)
 349                 panic("PMU Firmware device not found - Enable it");
 350 #endif
 351
 352 #if defined(CONFIG_SPL_BUILD)
 353         /* Check *at build time* if the filename is an non-empty string */
 354         if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
 355                 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
 356                                                 zynqmp_pm_cfg_obj_size);
 357 #endif
 358
 359         printf("EL Level:\tEL%d\n", current_el());
 360
 361 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 362     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
 363     defined(CONFIG_SPL_BUILD))
 364         if (current_el() != 3) {
 365                 zynqmppl.name = zynqmp_get_silicon_idcode_name();
 366                 printf("Chip ID:\t%s\n", zynqmppl.name);
 367                 fpga_init();
 368                 fpga_add(fpga_xilinx, &zynqmppl);
 369         }
 370 #endif
 371
 372         if (current_el() == 3)
 373                 multi_boot();
 374
 375         return 0;
 376 }
 377
 378 int board_early_init_r(void)
 379 {
 380         u32 val;
 381
 382         if (current_el() != 3)
 383                 return 0;
 384
 385         val = readl(&crlapb_base->timestamp_ref_ctrl);
 386         val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 387
 388         if (!val) {
 389                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 390                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 391                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 392
 393                 /* Program freq register in System counter */
 394                 writel(zynqmp_get_system_timer_freq(),
 395                        &iou_scntr_secure->base_frequency_id_register);
 396                 /* And enable system counter */
 397                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 398                        &iou_scntr_secure->counter_control_register);
 399         }
 400         return 0;
 401 }
 402
 403 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
 404                          char * const argv[])
 405 {
 406         int ret = 0;
 407
 408         if (current_el() > 1) {
 409                 smp_kick_all_cpus();
 410                 dcache_disable();
 411                 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
 412                                     ES_TO_AARCH64);
 413         } else {
 414                 printf("FAIL: current EL is not above EL1\n");
 415                 ret = EINVAL;
 416         }
 417         return ret;
 418 }
 419
 420 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 421 int dram_init_banksize(void)
 422 {
 423         int ret;
 424
 425         ret = fdtdec_setup_memory_banksize();
 426         if (ret)
 427                 return ret;
 428
 429         mem_map_fill();
 430
 431         return 0;
 432 }
 433
 434 int dram_init(void)
 435 {
 436         if (fdtdec_setup_mem_size_base() != 0)
 437                 return -EINVAL;
 438
 439         return 0;
 440 }
 441 #else
 442 int dram_init_banksize(void)
 443 {
 444 #if defined(CONFIG_NR_DRAM_BANKS)
 445         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 446         gd->bd->bi_dram[0].size = get_effective_memsize();
 447 #endif
 448
 449         mem_map_fill();
 450
 451         return 0;
 452 }
 453
 454 int dram_init(void)
 455 {
 456         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 457                                     CONFIG_SYS_SDRAM_SIZE);
 458
 459         return 0;
 460 }
 461 #endif
 462
 463 void reset_cpu(ulong addr)
 464 {
 465 }
 466
 467 #if defined(CONFIG_BOARD_LATE_INIT)
 468 static const struct {
 469         u32 bit;
 470         const char *name;
 471 } reset_reasons[] = {
 472         { RESET_REASON_DEBUG_SYS, "DEBUG" },
 473         { RESET_REASON_SOFT, "SOFT" },
 474         { RESET_REASON_SRST, "SRST" },
 475         { RESET_REASON_PSONLY, "PS-ONLY" },
 476         { RESET_REASON_PMU, "PMU" },
 477         { RESET_REASON_INTERNAL, "INTERNAL" },
 478         { RESET_REASON_EXTERNAL, "EXTERNAL" },
 479         {}
 480 };
 481
 482 static int reset_reason(void)
 483 {
 484         u32 reg;
 485         int i, ret;
 486         const char *reason = NULL;
 487
 488         ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
 489         if (ret)
 490                 return -EINVAL;
 491
 492         puts("Reset reason:\t");
 493
 494         for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
 495                 if (reg & reset_reasons[i].bit) {
 496                         reason = reset_reasons[i].name;
 497                         printf("%s ", reset_reasons[i].name);
 498                         break;
 499                 }
 500         }
 501
 502         puts("\n");
 503
 504         env_set("reset_reason", reason);
 505
 506         ret = zynqmp_mmio_write(~0, ~0, (ulong)&crlapb_base->reset_reason);
 507         if (ret)
 508                 return -EINVAL;
 509
 510         return ret;
 511 }
 512
 513 static int set_fdtfile(void)
 514 {
 515         char *compatible, *fdtfile;
 516         const char *suffix = ".dtb";
 517         const char *vendor = "xilinx/";
 518
 519         if (env_get("fdtfile"))
 520                 return 0;
 521
 522         compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
 523         if (compatible) {
 524                 debug("Compatible: %s\n", compatible);
 525
 526                 /* Discard vendor prefix */
 527                 strsep(&compatible, ",");
 528
 529                 fdtfile = calloc(1, strlen(vendor) + strlen(compatible) +
 530                                  strlen(suffix) + 1);
 531                 if (!fdtfile)
 532                         return -ENOMEM;
 533
 534                 sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix);
 535
 536                 env_set("fdtfile", fdtfile);
 537                 free(fdtfile);
 538         }
 539
 540         return 0;
 541 }
 542
 543 int board_late_init(void)
 544 {
 545         u32 reg = 0;
 546         u8 bootmode;
 547         struct udevice *dev;
 548         int bootseq = -1;
 549         int bootseq_len = 0;
 550         int env_targets_len = 0;
 551         const char *mode;
 552         char *new_targets;
 553         char *env_targets;
 554         int ret;
 555         ulong initrd_hi;
 556
 557 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
 558         usb_ether_init();
 559 #endif
 560
 561         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 562                 debug("Saved variables - Skipping\n");
 563                 return 0;
 564         }
 565
 566         ret = set_fdtfile();
 567         if (ret)
 568                 return ret;
 569
 570         ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
 571         if (ret)
 572                 return -EINVAL;
 573
 574         if (reg >> BOOT_MODE_ALT_SHIFT)
 575                 reg >>= BOOT_MODE_ALT_SHIFT;
 576
 577         bootmode = reg & BOOT_MODES_MASK;
 578
 579         puts("Bootmode: ");
 580         switch (bootmode) {
 581         case USB_MODE:
 582                 puts("USB_MODE\n");
 583                 mode = "usb";
 584                 env_set("modeboot", "usb_dfu_spl");
 585                 break;
 586         case JTAG_MODE:
 587                 puts("JTAG_MODE\n");
 588                 mode = "jtag pxe dhcp";
 589                 env_set("modeboot", "jtagboot");
 590                 break;
 591         case QSPI_MODE_24BIT:
 592         case QSPI_MODE_32BIT:
 593                 mode = "qspi0";
 594                 puts("QSPI_MODE\n");
 595                 env_set("modeboot", "qspiboot");
 596                 break;
 597         case EMMC_MODE:
 598                 puts("EMMC_MODE\n");
 599                 if (uclass_get_device_by_name(UCLASS_MMC,
 600                                               "mmc@ff160000", &dev) &&
 601                     uclass_get_device_by_name(UCLASS_MMC,
 602                                               "sdhci@ff160000", &dev)) {
 603                         puts("Boot from EMMC but without SD0 enabled!\n");
 604                         return -1;
 605                 }
 606                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 607
 608                 mode = "mmc";
 609                 bootseq = dev->seq;
 610                 break;
 611         case SD_MODE:
 612                 puts("SD_MODE\n");
 613                 if (uclass_get_device_by_name(UCLASS_MMC,
 614                                               "mmc@ff160000", &dev) &&
 615                     uclass_get_device_by_name(UCLASS_MMC,
 616                                               "sdhci@ff160000", &dev)) {
 617                         puts("Boot from SD0 but without SD0 enabled!\n");
 618                         return -1;
 619                 }
 620                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 621
 622                 mode = "mmc";
 623                 bootseq = dev->seq;
 624                 env_set("modeboot", "sdboot");
 625                 break;
 626         case SD1_LSHFT_MODE:
 627                 puts("LVL_SHFT_");
 628                 /* fall through */
 629         case SD_MODE1:
 630                 puts("SD_MODE1\n");
 631                 if (uclass_get_device_by_name(UCLASS_MMC,
 632                                               "mmc@ff170000", &dev) &&
 633                     uclass_get_device_by_name(UCLASS_MMC,
 634                                               "sdhci@ff170000", &dev)) {
 635                         puts("Boot from SD1 but without SD1 enabled!\n");
 636                         return -1;
 637                 }
 638                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 639
 640                 mode = "mmc";
 641                 bootseq = dev->seq;
 642                 env_set("modeboot", "sdboot");
 643                 break;
 644         case NAND_MODE:
 645                 puts("NAND_MODE\n");
 646                 mode = "nand0";
 647                 env_set("modeboot", "nandboot");
 648                 break;
 649         default:
 650                 mode = "";
 651                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 652                 break;
 653         }
 654
 655         if (bootseq >= 0) {
 656                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 657                 debug("Bootseq len: %x\n", bootseq_len);
 658         }
 659
 660         /*
 661          * One terminating char + one byte for space between mode
 662          * and default boot_targets
 663          */
 664         env_targets = env_get("boot_targets");
 665         if (env_targets)
 666                 env_targets_len = strlen(env_targets);
 667
 668         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 669                              bootseq_len);
 670         if (!new_targets)
 671                 return -ENOMEM;
 672
 673         if (bootseq >= 0)
 674                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 675                         env_targets ? env_targets : "");
 676         else
 677                 sprintf(new_targets, "%s %s", mode,
 678                         env_targets ? env_targets : "");
 679
 680         env_set("boot_targets", new_targets);
 681
 682         initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
 683         initrd_hi = round_down(initrd_hi, SZ_16M);
 684         env_set_addr("initrd_high", (void *)initrd_hi);
 685
 686         env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
 687
 688         reset_reason();
 689
 690         return 0;
 691 }
 692 #endif
 693
 694 int checkboard(void)
 695 {
 696         puts("Board: Xilinx ZynqMP\n");
 697         return 0;
 698 }