1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
14 #include <asm/arch/clk.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/arch/psu_init_gpl.h>
19 #include <dm/device.h>
20 #include <dm/uclass.h>
22 #include <dwc3-uboot.h>
24 #include <zynqmp_firmware.h>
26 #include <linux/sizes.h>
28 #include "pm_cfg_obj.h"
30 DECLARE_GLOBAL_DATA_PTR;
32 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
33 !defined(CONFIG_SPL_BUILD)
34 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
41 } zynqmp_devices[] = {
133 { /* For testing purpose only */
189 int chip_id(unsigned char id)
194 if (current_el() != 3) {
195 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
204 * regs[0][31:0] = status of the operation
205 * regs[0][63:32] = CSU.IDCODE register
206 * regs[1][31:0] = CSU.version register
207 * regs[1][63:32] = CSU.IDCODE2 register
211 regs.regs[0] = upper_32_bits(regs.regs[0]);
212 regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
213 ZYNQMP_CSU_IDCODE_SVD_MASK;
214 regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
218 regs.regs[1] = lower_32_bits(regs.regs[1]);
219 regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
223 regs.regs[1] = lower_32_bits(regs.regs[1]);
224 regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
228 printf("%s, Invalid Req:0x%x\n", __func__, id);
233 val = readl(ZYNQMP_CSU_IDCODE_ADDR);
234 val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
235 ZYNQMP_CSU_IDCODE_SVD_MASK;
236 val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
239 val = readl(ZYNQMP_CSU_VER_ADDR);
240 val &= ZYNQMP_CSU_SILICON_VER_MASK;
243 printf("%s, Invalid Req:0x%x\n", __func__, id);
250 #define ZYNQMP_VERSION_SIZE 9
251 #define ZYNQMP_PL_STATUS_BIT 9
252 #define ZYNQMP_IPDIS_VCU_BIT 8
253 #define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
254 #define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
255 #define ZYNQMP_CSU_VCUDIS_VER_MASK ZYNQMP_CSU_VERSION_MASK & \
256 ~BIT(ZYNQMP_IPDIS_VCU_BIT)
257 #define MAX_VARIANTS_EV 3
259 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
260 !defined(CONFIG_SPL_BUILD)
261 static char *zynqmp_get_silicon_idcode_name(void)
265 static char name[ZYNQMP_VERSION_SIZE];
267 id = chip_id(IDCODE);
268 ver = chip_id(IDCODE2);
270 for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
271 if (zynqmp_devices[i].id == id) {
272 if (zynqmp_devices[i].evexists &&
273 !(ver & ZYNQMP_PL_STATUS_MASK))
275 if (zynqmp_devices[i].ver == (ver &
276 ZYNQMP_CSU_VERSION_MASK))
281 if (i >= ARRAY_SIZE(zynqmp_devices))
284 strncat(name, "zu", 2);
285 if (!zynqmp_devices[i].evexists ||
286 (ver & ZYNQMP_PL_STATUS_MASK)) {
287 strncat(name, zynqmp_devices[i].name,
288 ZYNQMP_VERSION_SIZE - 3);
293 * Here we are means, PL not powered up and ev variant
294 * exists. So, we need to ignore VCU disable bit(8) in
295 * version and findout if its CG or EG/EV variant.
297 for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
298 if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
299 (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
300 strncat(name, zynqmp_devices[i].name,
301 ZYNQMP_VERSION_SIZE - 3);
306 if (j >= MAX_VARIANTS_EV)
309 if (strstr(name, "eg") || strstr(name, "ev")) {
310 buf = strstr(name, "e");
318 int board_early_init_f(void)
322 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
333 uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
335 panic("PMU Firmware device not found - Enable it");
337 #if defined(CONFIG_SPL_BUILD)
338 /* Check *at build time* if the filename is an non-empty string */
339 if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
340 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
341 zynqmp_pm_cfg_obj_size);
344 printf("EL Level:\tEL%d\n", current_el());
346 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
347 !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
348 defined(CONFIG_SPL_BUILD))
349 if (current_el() != 3) {
350 zynqmppl.name = zynqmp_get_silicon_idcode_name();
351 printf("Chip ID:\t%s\n", zynqmppl.name);
353 fpga_add(fpga_xilinx, &zynqmppl);
360 int board_early_init_r(void)
364 if (current_el() != 3)
367 val = readl(&crlapb_base->timestamp_ref_ctrl);
368 val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
371 val = readl(&crlapb_base->timestamp_ref_ctrl);
372 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
373 writel(val, &crlapb_base->timestamp_ref_ctrl);
375 /* Program freq register in System counter */
376 writel(zynqmp_get_system_timer_freq(),
377 &iou_scntr_secure->base_frequency_id_register);
378 /* And enable system counter */
379 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
380 &iou_scntr_secure->counter_control_register);
385 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
390 if (current_el() > 1) {
393 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
396 printf("FAIL: current EL is not above EL1\n");
402 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
403 int dram_init_banksize(void)
407 ret = fdtdec_setup_memory_banksize();
418 if (fdtdec_setup_mem_size_base() != 0)
424 int dram_init_banksize(void)
426 #if defined(CONFIG_NR_DRAM_BANKS)
427 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
428 gd->bd->bi_dram[0].size = get_effective_memsize();
438 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
439 CONFIG_SYS_SDRAM_SIZE);
445 void reset_cpu(ulong addr)
449 #if defined(CONFIG_BOARD_LATE_INIT)
450 static const struct {
453 } reset_reasons[] = {
454 { RESET_REASON_DEBUG_SYS, "DEBUG" },
455 { RESET_REASON_SOFT, "SOFT" },
456 { RESET_REASON_SRST, "SRST" },
457 { RESET_REASON_PSONLY, "PS-ONLY" },
458 { RESET_REASON_PMU, "PMU" },
459 { RESET_REASON_INTERNAL, "INTERNAL" },
460 { RESET_REASON_EXTERNAL, "EXTERNAL" },
464 static int reset_reason(void)
468 const char *reason = NULL;
470 ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, ®);
474 puts("Reset reason:\t");
476 for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
477 if (reg & reset_reasons[i].bit) {
478 reason = reset_reasons[i].name;
479 printf("%s ", reset_reasons[i].name);
486 env_set("reset_reason", reason);
488 ret = zynqmp_mmio_write(~0, ~0, (ulong)&crlapb_base->reset_reason);
495 static int set_fdtfile(void)
497 char *compatible, *fdtfile;
498 const char *suffix = ".dtb";
499 const char *vendor = "xilinx/";
501 if (env_get("fdtfile"))
504 compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
506 debug("Compatible: %s\n", compatible);
508 /* Discard vendor prefix */
509 strsep(&compatible, ",");
511 fdtfile = calloc(1, strlen(vendor) + strlen(compatible) +
516 sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix);
518 env_set("fdtfile", fdtfile);
525 int board_late_init(void)
532 int env_targets_len = 0;
539 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
543 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
544 debug("Saved variables - Skipping\n");
552 ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®);
556 if (reg >> BOOT_MODE_ALT_SHIFT)
557 reg >>= BOOT_MODE_ALT_SHIFT;
559 bootmode = reg & BOOT_MODES_MASK;
566 env_set("modeboot", "usb_dfu_spl");
570 mode = "jtag pxe dhcp";
571 env_set("modeboot", "jtagboot");
573 case QSPI_MODE_24BIT:
574 case QSPI_MODE_32BIT:
577 env_set("modeboot", "qspiboot");
582 env_set("modeboot", "emmcboot");
586 if (uclass_get_device_by_name(UCLASS_MMC,
587 "mmc@ff160000", &dev) &&
588 uclass_get_device_by_name(UCLASS_MMC,
589 "sdhci@ff160000", &dev)) {
590 puts("Boot from SD0 but without SD0 enabled!\n");
593 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
597 env_set("modeboot", "sdboot");
604 if (uclass_get_device_by_name(UCLASS_MMC,
605 "mmc@ff170000", &dev) &&
606 uclass_get_device_by_name(UCLASS_MMC,
607 "sdhci@ff170000", &dev)) {
608 puts("Boot from SD1 but without SD1 enabled!\n");
611 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
615 env_set("modeboot", "sdboot");
620 env_set("modeboot", "nandboot");
624 printf("Invalid Boot Mode:0x%x\n", bootmode);
629 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
630 debug("Bootseq len: %x\n", bootseq_len);
634 * One terminating char + one byte for space between mode
635 * and default boot_targets
637 env_targets = env_get("boot_targets");
639 env_targets_len = strlen(env_targets);
641 new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
647 sprintf(new_targets, "%s%x %s", mode, bootseq,
648 env_targets ? env_targets : "");
650 sprintf(new_targets, "%s %s", mode,
651 env_targets ? env_targets : "");
653 env_set("boot_targets", new_targets);
655 initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
656 initrd_hi = round_down(initrd_hi, SZ_16M);
657 env_set_addr("initrd_high", (void *)initrd_hi);
667 puts("Board: Xilinx ZynqMP\n");