1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
9 #include <debug_uart.h>
17 #include <asm/arch/clk.h>
18 #include <asm/arch/hardware.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/arch/psu_init_gpl.h>
22 #include <dm/device.h>
23 #include <dm/uclass.h>
25 #include <dwc3-uboot.h>
27 #include <zynqmp_firmware.h>
29 #include <linux/sizes.h>
30 #include "../common/board.h"
32 #include "pm_cfg_obj.h"
34 DECLARE_GLOBAL_DATA_PTR;
36 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
37 !defined(CONFIG_SPL_BUILD)
38 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
45 } zynqmp_devices[] = {
137 { /* For testing purpose only */
193 int chip_id(unsigned char id)
198 if (current_el() != 3) {
199 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
208 * regs[0][31:0] = status of the operation
209 * regs[0][63:32] = CSU.IDCODE register
210 * regs[1][31:0] = CSU.version register
211 * regs[1][63:32] = CSU.IDCODE2 register
215 regs.regs[0] = upper_32_bits(regs.regs[0]);
216 regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
217 ZYNQMP_CSU_IDCODE_SVD_MASK;
218 regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
222 regs.regs[1] = lower_32_bits(regs.regs[1]);
223 regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
227 regs.regs[1] = lower_32_bits(regs.regs[1]);
228 regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
232 printf("%s, Invalid Req:0x%x\n", __func__, id);
237 val = readl(ZYNQMP_CSU_IDCODE_ADDR);
238 val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
239 ZYNQMP_CSU_IDCODE_SVD_MASK;
240 val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
243 val = readl(ZYNQMP_CSU_VER_ADDR);
244 val &= ZYNQMP_CSU_SILICON_VER_MASK;
247 printf("%s, Invalid Req:0x%x\n", __func__, id);
254 #define ZYNQMP_VERSION_SIZE 9
255 #define ZYNQMP_PL_STATUS_BIT 9
256 #define ZYNQMP_IPDIS_VCU_BIT 8
257 #define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
258 #define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
259 #define ZYNQMP_CSU_VCUDIS_VER_MASK ZYNQMP_CSU_VERSION_MASK & \
260 ~BIT(ZYNQMP_IPDIS_VCU_BIT)
261 #define MAX_VARIANTS_EV 3
263 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
264 !defined(CONFIG_SPL_BUILD)
265 static char *zynqmp_get_silicon_idcode_name(void)
269 static char name[ZYNQMP_VERSION_SIZE];
271 id = chip_id(IDCODE);
272 ver = chip_id(IDCODE2);
274 for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
275 if (zynqmp_devices[i].id == id) {
276 if (zynqmp_devices[i].evexists &&
277 !(ver & ZYNQMP_PL_STATUS_MASK))
279 if (zynqmp_devices[i].ver == (ver &
280 ZYNQMP_CSU_VERSION_MASK))
285 if (i >= ARRAY_SIZE(zynqmp_devices))
288 strncat(name, "zu", 2);
289 if (!zynqmp_devices[i].evexists ||
290 (ver & ZYNQMP_PL_STATUS_MASK)) {
291 strncat(name, zynqmp_devices[i].name,
292 ZYNQMP_VERSION_SIZE - 3);
297 * Here we are means, PL not powered up and ev variant
298 * exists. So, we need to ignore VCU disable bit(8) in
299 * version and findout if its CG or EG/EV variant.
301 for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
302 if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
303 (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
304 strncat(name, zynqmp_devices[i].name,
305 ZYNQMP_VERSION_SIZE - 3);
310 if (j >= MAX_VARIANTS_EV)
313 if (strstr(name, "eg") || strstr(name, "ev")) {
314 buf = strstr(name, "e");
322 int board_early_init_f(void)
324 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
331 /* Delay is required for clocks to be propagated */
335 #ifdef CONFIG_DEBUG_UART
336 /* Uart debug for sure */
338 puts("Debug uart enabled\n"); /* or printch() */
344 static int multi_boot(void)
348 multiboot = readl(&csu_base->multi_boot);
350 printf("Multiboot:\t%x\n", multiboot);
357 #if defined(CONFIG_ZYNQMP_FIRMWARE)
360 uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
362 panic("PMU Firmware device not found - Enable it");
365 #if defined(CONFIG_SPL_BUILD)
366 /* Check *at build time* if the filename is an non-empty string */
367 if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
368 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
369 zynqmp_pm_cfg_obj_size);
372 printf("EL Level:\tEL%d\n", current_el());
374 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
375 !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
376 defined(CONFIG_SPL_BUILD))
377 if (current_el() != 3) {
378 zynqmppl.name = zynqmp_get_silicon_idcode_name();
379 printf("Chip ID:\t%s\n", zynqmppl.name);
381 fpga_add(fpga_xilinx, &zynqmppl);
385 if (current_el() == 3)
391 int board_early_init_r(void)
395 if (current_el() != 3)
398 val = readl(&crlapb_base->timestamp_ref_ctrl);
399 val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
402 val = readl(&crlapb_base->timestamp_ref_ctrl);
403 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
404 writel(val, &crlapb_base->timestamp_ref_ctrl);
406 /* Program freq register in System counter */
407 writel(zynqmp_get_system_timer_freq(),
408 &iou_scntr_secure->base_frequency_id_register);
409 /* And enable system counter */
410 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
411 &iou_scntr_secure->counter_control_register);
416 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
421 if (current_el() > 1) {
424 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
427 printf("FAIL: current EL is not above EL1\n");
433 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
434 int dram_init_banksize(void)
438 ret = fdtdec_setup_memory_banksize();
449 if (fdtdec_setup_mem_size_base() != 0)
455 int dram_init_banksize(void)
457 #if defined(CONFIG_NR_DRAM_BANKS)
458 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
459 gd->bd->bi_dram[0].size = get_effective_memsize();
469 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
470 CONFIG_SYS_SDRAM_SIZE);
476 void reset_cpu(ulong addr)
480 #if defined(CONFIG_BOARD_LATE_INIT)
481 static const struct {
484 } reset_reasons[] = {
485 { RESET_REASON_DEBUG_SYS, "DEBUG" },
486 { RESET_REASON_SOFT, "SOFT" },
487 { RESET_REASON_SRST, "SRST" },
488 { RESET_REASON_PSONLY, "PS-ONLY" },
489 { RESET_REASON_PMU, "PMU" },
490 { RESET_REASON_INTERNAL, "INTERNAL" },
491 { RESET_REASON_EXTERNAL, "EXTERNAL" },
495 static int reset_reason(void)
499 const char *reason = NULL;
501 ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, ®);
505 puts("Reset reason:\t");
507 for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
508 if (reg & reset_reasons[i].bit) {
509 reason = reset_reasons[i].name;
510 printf("%s ", reset_reasons[i].name);
517 env_set("reset_reason", reason);
519 ret = zynqmp_mmio_write((ulong)&crlapb_base->reset_reason, ~0, ~0);
526 static int set_fdtfile(void)
528 char *compatible, *fdtfile;
529 const char *suffix = ".dtb";
530 const char *vendor = "xilinx/";
532 if (env_get("fdtfile"))
535 compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
537 debug("Compatible: %s\n", compatible);
539 /* Discard vendor prefix */
540 strsep(&compatible, ",");
542 fdtfile = calloc(1, strlen(vendor) + strlen(compatible) +
547 sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix);
549 env_set("fdtfile", fdtfile);
556 int board_late_init(void)
563 int env_targets_len = 0;
570 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
574 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
575 debug("Saved variables - Skipping\n");
583 ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®);
587 if (reg >> BOOT_MODE_ALT_SHIFT)
588 reg >>= BOOT_MODE_ALT_SHIFT;
590 bootmode = reg & BOOT_MODES_MASK;
597 env_set("modeboot", "usb_dfu_spl");
601 mode = "jtag pxe dhcp";
602 env_set("modeboot", "jtagboot");
604 case QSPI_MODE_24BIT:
605 case QSPI_MODE_32BIT:
608 env_set("modeboot", "qspiboot");
612 if (uclass_get_device_by_name(UCLASS_MMC,
613 "mmc@ff160000", &dev) &&
614 uclass_get_device_by_name(UCLASS_MMC,
615 "sdhci@ff160000", &dev)) {
616 puts("Boot from EMMC but without SD0 enabled!\n");
619 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
626 if (uclass_get_device_by_name(UCLASS_MMC,
627 "mmc@ff160000", &dev) &&
628 uclass_get_device_by_name(UCLASS_MMC,
629 "sdhci@ff160000", &dev)) {
630 puts("Boot from SD0 but without SD0 enabled!\n");
633 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
637 env_set("modeboot", "sdboot");
644 if (uclass_get_device_by_name(UCLASS_MMC,
645 "mmc@ff170000", &dev) &&
646 uclass_get_device_by_name(UCLASS_MMC,
647 "sdhci@ff170000", &dev)) {
648 puts("Boot from SD1 but without SD1 enabled!\n");
651 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
655 env_set("modeboot", "sdboot");
660 env_set("modeboot", "nandboot");
664 printf("Invalid Boot Mode:0x%x\n", bootmode);
669 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
670 debug("Bootseq len: %x\n", bootseq_len);
674 * One terminating char + one byte for space between mode
675 * and default boot_targets
677 env_targets = env_get("boot_targets");
679 env_targets_len = strlen(env_targets);
681 new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
687 sprintf(new_targets, "%s%x %s", mode, bootseq,
688 env_targets ? env_targets : "");
690 sprintf(new_targets, "%s %s", mode,
691 env_targets ? env_targets : "");
693 env_set("boot_targets", new_targets);
695 initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
696 initrd_hi = round_down(initrd_hi, SZ_16M);
697 env_set_addr("initrd_high", (void *)initrd_hi);
701 return board_late_init_xilinx();
707 puts("Board: Xilinx ZynqMP\n");