board/xilinx/zynqmp/zynqmp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <env.h>
   9 #include <sata.h>
  10 #include <ahci.h>
  11 #include <scsi.h>
  12 #include <malloc.h>
  13 #include <wdt.h>
  14 #include <asm/arch/clk.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/arch/psu_init_gpl.h>
  18 #include <asm/io.h>
  19 #include <dm/device.h>
  20 #include <dm/uclass.h>
  21 #include <usb.h>
  22 #include <dwc3-uboot.h>
  23 #include <zynqmppl.h>
  24 #include <g_dnl.h>
  25 #include <linux/sizes.h>
  26
  27 #include "pm_cfg_obj.h"
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  32     !defined(CONFIG_SPL_BUILD)
  33 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  34
  35 static const struct {
  36         u32 id;
  37         u32 ver;
  38         char *name;
  39         bool evexists;
  40 } zynqmp_devices[] = {
  41         {
  42                 .id = 0x10,
  43                 .name = "3eg",
  44         },
  45         {
  46                 .id = 0x10,
  47                 .ver = 0x2c,
  48                 .name = "3cg",
  49         },
  50         {
  51                 .id = 0x11,
  52                 .name = "2eg",
  53         },
  54         {
  55                 .id = 0x11,
  56                 .ver = 0x2c,
  57                 .name = "2cg",
  58         },
  59         {
  60                 .id = 0x20,
  61                 .name = "5ev",
  62                 .evexists = 1,
  63         },
  64         {
  65                 .id = 0x20,
  66                 .ver = 0x100,
  67                 .name = "5eg",
  68                 .evexists = 1,
  69         },
  70         {
  71                 .id = 0x20,
  72                 .ver = 0x12c,
  73                 .name = "5cg",
  74                 .evexists = 1,
  75         },
  76         {
  77                 .id = 0x21,
  78                 .name = "4ev",
  79                 .evexists = 1,
  80         },
  81         {
  82                 .id = 0x21,
  83                 .ver = 0x100,
  84                 .name = "4eg",
  85                 .evexists = 1,
  86         },
  87         {
  88                 .id = 0x21,
  89                 .ver = 0x12c,
  90                 .name = "4cg",
  91                 .evexists = 1,
  92         },
  93         {
  94                 .id = 0x30,
  95                 .name = "7ev",
  96                 .evexists = 1,
  97         },
  98         {
  99                 .id = 0x30,
 100                 .ver = 0x100,
 101                 .name = "7eg",
 102                 .evexists = 1,
 103         },
 104         {
 105                 .id = 0x30,
 106                 .ver = 0x12c,
 107                 .name = "7cg",
 108                 .evexists = 1,
 109         },
 110         {
 111                 .id = 0x38,
 112                 .name = "9eg",
 113         },
 114         {
 115                 .id = 0x38,
 116                 .ver = 0x2c,
 117                 .name = "9cg",
 118         },
 119         {
 120                 .id = 0x39,
 121                 .name = "6eg",
 122         },
 123         {
 124                 .id = 0x39,
 125                 .ver = 0x2c,
 126                 .name = "6cg",
 127         },
 128         {
 129                 .id = 0x40,
 130                 .name = "11eg",
 131         },
 132         { /* For testing purpose only */
 133                 .id = 0x50,
 134                 .ver = 0x2c,
 135                 .name = "15cg",
 136         },
 137         {
 138                 .id = 0x50,
 139                 .name = "15eg",
 140         },
 141         {
 142                 .id = 0x58,
 143                 .name = "19eg",
 144         },
 145         {
 146                 .id = 0x59,
 147                 .name = "17eg",
 148         },
 149         {
 150                 .id = 0x61,
 151                 .name = "21dr",
 152         },
 153         {
 154                 .id = 0x63,
 155                 .name = "23dr",
 156         },
 157         {
 158                 .id = 0x65,
 159                 .name = "25dr",
 160         },
 161         {
 162                 .id = 0x64,
 163                 .name = "27dr",
 164         },
 165         {
 166                 .id = 0x60,
 167                 .name = "28dr",
 168         },
 169         {
 170                 .id = 0x62,
 171                 .name = "29dr",
 172         },
 173         {
 174                 .id = 0x66,
 175                 .name = "39dr",
 176         },
 177         {
 178                 .id = 0x7b,
 179                 .name = "48dr",
 180         },
 181         {
 182                 .id = 0x7e,
 183                 .name = "49dr",
 184         },
 185 };
 186 #endif
 187
 188 int chip_id(unsigned char id)
 189 {
 190         struct pt_regs regs;
 191         int val = -EINVAL;
 192
 193         if (current_el() != 3) {
 194                 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
 195                 regs.regs[1] = 0;
 196                 regs.regs[2] = 0;
 197                 regs.regs[3] = 0;
 198
 199                 smc_call(&regs);
 200
 201                 /*
 202                  * SMC returns:
 203                  * regs[0][31:0]  = status of the operation
 204                  * regs[0][63:32] = CSU.IDCODE register
 205                  * regs[1][31:0]  = CSU.version register
 206                  * regs[1][63:32] = CSU.IDCODE2 register
 207                  */
 208                 switch (id) {
 209                 case IDCODE:
 210                         regs.regs[0] = upper_32_bits(regs.regs[0]);
 211                         regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 212                                         ZYNQMP_CSU_IDCODE_SVD_MASK;
 213                         regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 214                         val = regs.regs[0];
 215                         break;
 216                 case VERSION:
 217                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 218                         regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
 219                         val = regs.regs[1];
 220                         break;
 221                 case IDCODE2:
 222                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 223                         regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
 224                         val = regs.regs[1];
 225                         break;
 226                 default:
 227                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 228                 }
 229         } else {
 230                 switch (id) {
 231                 case IDCODE:
 232                         val = readl(ZYNQMP_CSU_IDCODE_ADDR);
 233                         val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 234                                ZYNQMP_CSU_IDCODE_SVD_MASK;
 235                         val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 236                         break;
 237                 case VERSION:
 238                         val = readl(ZYNQMP_CSU_VER_ADDR);
 239                         val &= ZYNQMP_CSU_SILICON_VER_MASK;
 240                         break;
 241                 default:
 242                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 243                 }
 244         }
 245
 246         return val;
 247 }
 248
 249 #define ZYNQMP_VERSION_SIZE             9
 250 #define ZYNQMP_PL_STATUS_BIT            9
 251 #define ZYNQMP_IPDIS_VCU_BIT            8
 252 #define ZYNQMP_PL_STATUS_MASK           BIT(ZYNQMP_PL_STATUS_BIT)
 253 #define ZYNQMP_CSU_VERSION_MASK         ~(ZYNQMP_PL_STATUS_MASK)
 254 #define ZYNQMP_CSU_VCUDIS_VER_MASK      ZYNQMP_CSU_VERSION_MASK & \
 255                                         ~BIT(ZYNQMP_IPDIS_VCU_BIT)
 256 #define MAX_VARIANTS_EV                 3
 257
 258 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 259         !defined(CONFIG_SPL_BUILD)
 260 static char *zynqmp_get_silicon_idcode_name(void)
 261 {
 262         u32 i, id, ver, j;
 263         char *buf;
 264         static char name[ZYNQMP_VERSION_SIZE];
 265
 266         id = chip_id(IDCODE);
 267         ver = chip_id(IDCODE2);
 268
 269         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 270                 if (zynqmp_devices[i].id == id) {
 271                         if (zynqmp_devices[i].evexists &&
 272                             !(ver & ZYNQMP_PL_STATUS_MASK))
 273                                 break;
 274                         if (zynqmp_devices[i].ver == (ver &
 275                             ZYNQMP_CSU_VERSION_MASK))
 276                                 break;
 277                 }
 278         }
 279
 280         if (i >= ARRAY_SIZE(zynqmp_devices))
 281                 return "unknown";
 282
 283         strncat(name, "zu", 2);
 284         if (!zynqmp_devices[i].evexists ||
 285             (ver & ZYNQMP_PL_STATUS_MASK)) {
 286                 strncat(name, zynqmp_devices[i].name,
 287                         ZYNQMP_VERSION_SIZE - 3);
 288                 return name;
 289         }
 290
 291         /*
 292          * Here we are means, PL not powered up and ev variant
 293          * exists. So, we need to ignore VCU disable bit(8) in
 294          * version and findout if its CG or EG/EV variant.
 295          */
 296         for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
 297                 if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
 298                     (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
 299                         strncat(name, zynqmp_devices[i].name,
 300                                 ZYNQMP_VERSION_SIZE - 3);
 301                         break;
 302                 }
 303         }
 304
 305         if (j >= MAX_VARIANTS_EV)
 306                 return "unknown";
 307
 308         if (strstr(name, "eg") || strstr(name, "ev")) {
 309                 buf = strstr(name, "e");
 310                 *buf = '\0';
 311         }
 312
 313         return name;
 314 }
 315 #endif
 316
 317 int board_early_init_f(void)
 318 {
 319         int ret = 0;
 320 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
 321         u32 pm_api_version;
 322
 323         pm_api_version = zynqmp_pmufw_version();
 324         printf("PMUFW:\tv%d.%d\n",
 325                pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
 326                pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK);
 327
 328         if (pm_api_version < ZYNQMP_PM_VERSION)
 329                 panic("PMUFW version error. Expected: v%d.%d\n",
 330                       ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
 331 #endif
 332
 333 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 334         ret = psu_init();
 335 #endif
 336
 337         return ret;
 338 }
 339
 340 int board_init(void)
 341 {
 342 #if defined(CONFIG_SPL_BUILD)
 343         /* Check *at build time* if the filename is an non-empty string */
 344         if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
 345                 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
 346                                                 zynqmp_pm_cfg_obj_size);
 347 #endif
 348
 349         printf("EL Level:\tEL%d\n", current_el());
 350
 351 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 352     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
 353     defined(CONFIG_SPL_BUILD))
 354         if (current_el() != 3) {
 355                 zynqmppl.name = zynqmp_get_silicon_idcode_name();
 356                 printf("Chip ID:\t%s\n", zynqmppl.name);
 357                 fpga_init();
 358                 fpga_add(fpga_xilinx, &zynqmppl);
 359         }
 360 #endif
 361
 362         return 0;
 363 }
 364
 365 int board_early_init_r(void)
 366 {
 367         u32 val;
 368
 369         if (current_el() != 3)
 370                 return 0;
 371
 372         val = readl(&crlapb_base->timestamp_ref_ctrl);
 373         val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 374
 375         if (!val) {
 376                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 377                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 378                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 379
 380                 /* Program freq register in System counter */
 381                 writel(zynqmp_get_system_timer_freq(),
 382                        &iou_scntr_secure->base_frequency_id_register);
 383                 /* And enable system counter */
 384                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 385                        &iou_scntr_secure->counter_control_register);
 386         }
 387         return 0;
 388 }
 389
 390 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
 391                          char * const argv[])
 392 {
 393         int ret = 0;
 394
 395         if (current_el() > 1) {
 396                 smp_kick_all_cpus();
 397                 dcache_disable();
 398                 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
 399                                     ES_TO_AARCH64);
 400         } else {
 401                 printf("FAIL: current EL is not above EL1\n");
 402                 ret = EINVAL;
 403         }
 404         return ret;
 405 }
 406
 407 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 408 int dram_init_banksize(void)
 409 {
 410         int ret;
 411
 412         ret = fdtdec_setup_memory_banksize();
 413         if (ret)
 414                 return ret;
 415
 416         mem_map_fill();
 417
 418         return 0;
 419 }
 420
 421 int dram_init(void)
 422 {
 423         if (fdtdec_setup_mem_size_base() != 0)
 424                 return -EINVAL;
 425
 426         return 0;
 427 }
 428 #else
 429 int dram_init_banksize(void)
 430 {
 431 #if defined(CONFIG_NR_DRAM_BANKS)
 432         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 433         gd->bd->bi_dram[0].size = get_effective_memsize();
 434 #endif
 435
 436         mem_map_fill();
 437
 438         return 0;
 439 }
 440
 441 int dram_init(void)
 442 {
 443         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 444                                     CONFIG_SYS_SDRAM_SIZE);
 445
 446         return 0;
 447 }
 448 #endif
 449
 450 void reset_cpu(ulong addr)
 451 {
 452 }
 453
 454 #if defined(CONFIG_BOARD_LATE_INIT)
 455 static const struct {
 456         u32 bit;
 457         const char *name;
 458 } reset_reasons[] = {
 459         { RESET_REASON_DEBUG_SYS, "DEBUG" },
 460         { RESET_REASON_SOFT, "SOFT" },
 461         { RESET_REASON_SRST, "SRST" },
 462         { RESET_REASON_PSONLY, "PS-ONLY" },
 463         { RESET_REASON_PMU, "PMU" },
 464         { RESET_REASON_INTERNAL, "INTERNAL" },
 465         { RESET_REASON_EXTERNAL, "EXTERNAL" },
 466         {}
 467 };
 468
 469 static int reset_reason(void)
 470 {
 471         u32 reg;
 472         int i, ret;
 473         const char *reason = NULL;
 474
 475         ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
 476         if (ret)
 477                 return -EINVAL;
 478
 479         puts("Reset reason:\t");
 480
 481         for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
 482                 if (reg & reset_reasons[i].bit) {
 483                         reason = reset_reasons[i].name;
 484                         printf("%s ", reset_reasons[i].name);
 485                         break;
 486                 }
 487         }
 488
 489         puts("\n");
 490
 491         env_set("reset_reason", reason);
 492
 493         ret = zynqmp_mmio_write(~0, ~0, (ulong)&crlapb_base->reset_reason);
 494         if (ret)
 495                 return -EINVAL;
 496
 497         return ret;
 498 }
 499
 500 static int set_fdtfile(void)
 501 {
 502         char *compatible, *fdtfile;
 503         const char *suffix = ".dtb";
 504         const char *vendor = "xilinx/";
 505
 506         if (env_get("fdtfile"))
 507                 return 0;
 508
 509         compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
 510         if (compatible) {
 511                 debug("Compatible: %s\n", compatible);
 512
 513                 /* Discard vendor prefix */
 514                 strsep(&compatible, ",");
 515
 516                 fdtfile = calloc(1, strlen(vendor) + strlen(compatible) +
 517                                  strlen(suffix) + 1);
 518                 if (!fdtfile)
 519                         return -ENOMEM;
 520
 521                 sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix);
 522
 523                 env_set("fdtfile", fdtfile);
 524                 free(fdtfile);
 525         }
 526
 527         return 0;
 528 }
 529
 530 int board_late_init(void)
 531 {
 532         u32 reg = 0;
 533         u8 bootmode;
 534         struct udevice *dev;
 535         int bootseq = -1;
 536         int bootseq_len = 0;
 537         int env_targets_len = 0;
 538         const char *mode;
 539         char *new_targets;
 540         char *env_targets;
 541         int ret;
 542         ulong initrd_hi;
 543
 544 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
 545         usb_ether_init();
 546 #endif
 547
 548         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 549                 debug("Saved variables - Skipping\n");
 550                 return 0;
 551         }
 552
 553         ret = set_fdtfile();
 554         if (ret)
 555                 return ret;
 556
 557         ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
 558         if (ret)
 559                 return -EINVAL;
 560
 561         if (reg >> BOOT_MODE_ALT_SHIFT)
 562                 reg >>= BOOT_MODE_ALT_SHIFT;
 563
 564         bootmode = reg & BOOT_MODES_MASK;
 565
 566         puts("Bootmode: ");
 567         switch (bootmode) {
 568         case USB_MODE:
 569                 puts("USB_MODE\n");
 570                 mode = "usb";
 571                 env_set("modeboot", "usb_dfu_spl");
 572                 break;
 573         case JTAG_MODE:
 574                 puts("JTAG_MODE\n");
 575                 mode = "jtag pxe dhcp";
 576                 env_set("modeboot", "jtagboot");
 577                 break;
 578         case QSPI_MODE_24BIT:
 579         case QSPI_MODE_32BIT:
 580                 mode = "qspi0";
 581                 puts("QSPI_MODE\n");
 582                 env_set("modeboot", "qspiboot");
 583                 break;
 584         case EMMC_MODE:
 585                 puts("EMMC_MODE\n");
 586                 mode = "mmc0";
 587                 env_set("modeboot", "emmcboot");
 588                 break;
 589         case SD_MODE:
 590                 puts("SD_MODE\n");
 591                 if (uclass_get_device_by_name(UCLASS_MMC,
 592                                               "mmc@ff160000", &dev) &&
 593                     uclass_get_device_by_name(UCLASS_MMC,
 594                                               "sdhci@ff160000", &dev)) {
 595                         puts("Boot from SD0 but without SD0 enabled!\n");
 596                         return -1;
 597                 }
 598                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 599
 600                 mode = "mmc";
 601                 bootseq = dev->seq;
 602                 env_set("modeboot", "sdboot");
 603                 break;
 604         case SD1_LSHFT_MODE:
 605                 puts("LVL_SHFT_");
 606                 /* fall through */
 607         case SD_MODE1:
 608                 puts("SD_MODE1\n");
 609                 if (uclass_get_device_by_name(UCLASS_MMC,
 610                                               "mmc@ff170000", &dev) &&
 611                     uclass_get_device_by_name(UCLASS_MMC,
 612                                               "sdhci@ff170000", &dev)) {
 613                         puts("Boot from SD1 but without SD1 enabled!\n");
 614                         return -1;
 615                 }
 616                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 617
 618                 mode = "mmc";
 619                 bootseq = dev->seq;
 620                 env_set("modeboot", "sdboot");
 621                 break;
 622         case NAND_MODE:
 623                 puts("NAND_MODE\n");
 624                 mode = "nand0";
 625                 env_set("modeboot", "nandboot");
 626                 break;
 627         default:
 628                 mode = "";
 629                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 630                 break;
 631         }
 632
 633         if (bootseq >= 0) {
 634                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 635                 debug("Bootseq len: %x\n", bootseq_len);
 636         }
 637
 638         /*
 639          * One terminating char + one byte for space between mode
 640          * and default boot_targets
 641          */
 642         env_targets = env_get("boot_targets");
 643         if (env_targets)
 644                 env_targets_len = strlen(env_targets);
 645
 646         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 647                              bootseq_len);
 648         if (!new_targets)
 649                 return -ENOMEM;
 650
 651         if (bootseq >= 0)
 652                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 653                         env_targets ? env_targets : "");
 654         else
 655                 sprintf(new_targets, "%s %s", mode,
 656                         env_targets ? env_targets : "");
 657
 658         env_set("boot_targets", new_targets);
 659
 660         initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
 661         initrd_hi = round_down(initrd_hi, SZ_16M);
 662         env_set_addr("initrd_high", (void *)initrd_hi);
 663
 664         reset_reason();
 665
 666         return 0;
 667 }
 668 #endif
 669
 670 int checkboard(void)
 671 {
 672         puts("Board: Xilinx ZynqMP\n");
 673         return 0;
 674 }