2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/clk.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/sys_proto.h>
18 #include <dwc3-uboot.h>
22 DECLARE_GLOBAL_DATA_PTR;
26 printf("EL Level:\tEL%d\n", current_el());
31 int board_early_init_r(void)
35 if (current_el() == 3) {
36 val = readl(&crlapb_base->timestamp_ref_ctrl);
37 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
38 writel(val, &crlapb_base->timestamp_ref_ctrl);
40 /* Program freq register in System counter */
41 writel(zynqmp_get_system_timer_freq(),
42 &iou_scntr_secure->base_frequency_id_register);
43 /* And enable system counter */
44 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
45 &iou_scntr_secure->counter_control_register);
47 /* Program freq register in System counter and enable system counter */
48 writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
49 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
50 ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
51 &iou_scntr->counter_control_register);
56 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
58 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
59 defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
60 defined(CONFIG_ZYNQ_EEPROM_BUS)
61 i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
63 if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
64 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
66 printf("I2C EEPROM MAC address read failed\n");
72 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
74 * fdt_get_reg - Fill buffer by information from DT
76 static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
77 const u32 *cell, int n)
80 int parent_offset = fdt_parent_offset(fdt, nodeoffset);
81 int address_cells = fdt_address_cells(fdt, parent_offset);
82 int size_cells = fdt_size_cells(fdt, parent_offset);
87 debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
88 __func__, address_cells, size_cells, buf, cell);
90 /* Check memory bank setup */
91 banks = n % (address_cells + size_cells);
93 panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
94 n, address_cells, size_cells);
96 banks = n / (address_cells + size_cells);
98 for (b = 0; b < banks; b++) {
99 debug("%s: Bank #%d:\n", __func__, b);
100 if (address_cells == 2) {
104 val = fdt64_to_cpu(val);
105 debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
106 __func__, val, p, &cell[i]);
107 *(phys_addr_t *)p = val;
109 debug("%s: addr32=%x, ptr=%p\n",
110 __func__, fdt32_to_cpu(cell[i]), p);
111 *(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
113 p += sizeof(phys_addr_t);
116 debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
117 sizeof(phys_addr_t));
119 if (size_cells == 2) {
123 vals = fdt64_to_cpu(vals);
125 debug("%s: size64=%llx, ptr=%p, cell=%p\n",
126 __func__, vals, p, &cell[i]);
127 *(phys_size_t *)p = vals;
129 debug("%s: size32=%x, ptr=%p\n",
130 __func__, fdt32_to_cpu(cell[i]), p);
131 *(phys_size_t *)p = fdt32_to_cpu(cell[i]);
133 p += sizeof(phys_size_t);
136 debug("%s: ps=%p, i=%x, size=%zu\n",
137 __func__, p, i, sizeof(phys_size_t));
140 /* Return the first address size */
141 return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
144 #define FDT_REG_SIZE sizeof(u32)
145 /* Temp location for sharing data for storing */
146 /* Up to 64-bit address + 64-bit size */
147 static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
149 void dram_init_banksize(void)
153 memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
155 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
156 debug("Bank #%d: start %llx\n", bank,
157 (unsigned long long)gd->bd->bi_dram[bank].start);
158 debug("Bank #%d: size %llx\n", bank,
159 (unsigned long long)gd->bd->bi_dram[bank].size);
166 const void *blob = gd->fdt_blob;
169 memset(&tmp, 0, sizeof(tmp));
171 /* find or create "/memory" node. */
172 node = fdt_subnode_offset(blob, 0, "memory");
174 printf("%s: Can't get memory node\n", __func__);
178 /* Get pointer to cells and lenght of it */
179 cell = fdt_getprop(blob, node, "reg", &len);
181 printf("%s: Can't get reg property\n", __func__);
185 gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
187 debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
194 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
200 void reset_cpu(ulong addr)
204 #ifdef CONFIG_SCSI_AHCI_PLAT
207 #if defined(CONFIG_SATA_CEVA)
210 ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
215 int board_late_init(void)
222 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
223 debug("Saved variables - Skipping\n");
227 reg = readl(&crlapb_base->boot_mode);
228 bootmode = reg & BOOT_MODES_MASK;
236 case QSPI_MODE_24BIT:
237 case QSPI_MODE_32BIT:
251 #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
263 printf("Invalid Boot Mode:0x%x\n", bootmode);
268 * One terminating char + one byte for space between mode
269 * and default boot_targets
271 new_targets = calloc(1, strlen(mode) +
272 strlen(getenv("boot_targets")) + 2);
274 sprintf(new_targets, "%s %s", mode, getenv("boot_targets"));
275 setenv("boot_targets", new_targets);
282 puts("Board: Xilinx ZynqMP\n");
286 #ifdef CONFIG_USB_DWC3
287 static struct dwc3_device dwc3_device_data0 = {
288 .maximum_speed = USB_SPEED_HIGH,
289 .base = ZYNQMP_USB0_XHCI_BASEADDR,
290 .dr_mode = USB_DR_MODE_PERIPHERAL,
294 static struct dwc3_device dwc3_device_data1 = {
295 .maximum_speed = USB_SPEED_HIGH,
296 .base = ZYNQMP_USB1_XHCI_BASEADDR,
297 .dr_mode = USB_DR_MODE_PERIPHERAL,
301 int usb_gadget_handle_interrupts(int index)
303 dwc3_uboot_handle_interrupt(index);
307 int board_usb_init(int index, enum usb_init_type init)
309 debug("%s: index %x\n", __func__, index);
313 return dwc3_uboot_init(&dwc3_device_data0);
315 return dwc3_uboot_init(&dwc3_device_data1);
321 int board_usb_cleanup(int index, enum usb_init_type init)
323 dwc3_uboot_exit(index);
328 void reset_misc(void)
330 psci_system_reset(true);