2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/hardware.h>
13 #include <asm/arch/sys_proto.h>
16 DECLARE_GLOBAL_DATA_PTR;
20 printf("EL Level:\tEL%d\n", current_el());
25 int board_early_init_r(void)
29 val = readl(&crlapb_base->timestamp_ref_ctrl);
30 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
31 writel(val, &crlapb_base->timestamp_ref_ctrl);
33 /* Program freq register in System counter and enable system counter */
34 writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
35 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
36 ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
37 &iou_scntr->counter_control_register);
44 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
54 void reset_cpu(ulong addr)
58 #ifdef CONFIG_SCSI_AHCI_PLAT
61 ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
66 int board_eth_init(bd_t *bis)
70 #if defined(CONFIG_ZYNQ_GEM)
71 # if defined(CONFIG_ZYNQ_GEM0)
72 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
73 CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
75 # if defined(CONFIG_ZYNQ_GEM1)
76 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
77 CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
79 # if defined(CONFIG_ZYNQ_GEM2)
80 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR2,
81 CONFIG_ZYNQ_GEM_PHY_ADDR2, 0);
83 # if defined(CONFIG_ZYNQ_GEM3)
84 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR3,
85 CONFIG_ZYNQ_GEM_PHY_ADDR3, 0);
92 int board_mmc_init(bd_t *bd)
96 u32 ver = zynqmp_get_silicon_version();
98 if (ver != ZYNQMP_CSU_VERSION_VELOCE) {
99 #if defined(CONFIG_ZYNQ_SDHCI)
100 # if defined(CONFIG_ZYNQ_SDHCI0)
101 ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
103 # if defined(CONFIG_ZYNQ_SDHCI1)
104 ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
113 int board_late_init(void)
118 reg = readl(&crlapb_base->boot_mode);
119 bootmode = reg & BOOT_MODES_MASK;
124 setenv("modeboot", "sdboot");
127 printf("Invalid Boot Mode:0x%x\n", bootmode);