1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
13 #include <asm/arch/clk.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/arch/psu_init_gpl.h>
18 #include <dm/device.h>
19 #include <dm/uclass.h>
21 #include <dwc3-uboot.h>
25 #include "pm_cfg_obj.h"
27 DECLARE_GLOBAL_DATA_PTR;
29 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
30 !defined(CONFIG_SPL_BUILD)
31 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
38 } zynqmp_devices[] = {
130 { /* For testing purpose only */
178 int chip_id(unsigned char id)
183 if (current_el() != 3) {
184 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
193 * regs[0][31:0] = status of the operation
194 * regs[0][63:32] = CSU.IDCODE register
195 * regs[1][31:0] = CSU.version register
196 * regs[1][63:32] = CSU.IDCODE2 register
200 regs.regs[0] = upper_32_bits(regs.regs[0]);
201 regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
202 ZYNQMP_CSU_IDCODE_SVD_MASK;
203 regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
207 regs.regs[1] = lower_32_bits(regs.regs[1]);
208 regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
212 regs.regs[1] = lower_32_bits(regs.regs[1]);
213 regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
217 printf("%s, Invalid Req:0x%x\n", __func__, id);
222 val = readl(ZYNQMP_CSU_IDCODE_ADDR);
223 val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
224 ZYNQMP_CSU_IDCODE_SVD_MASK;
225 val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
228 val = readl(ZYNQMP_CSU_VER_ADDR);
229 val &= ZYNQMP_CSU_SILICON_VER_MASK;
232 printf("%s, Invalid Req:0x%x\n", __func__, id);
239 #define ZYNQMP_VERSION_SIZE 9
240 #define ZYNQMP_PL_STATUS_BIT 9
241 #define ZYNQMP_IPDIS_VCU_BIT 8
242 #define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
243 #define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
244 #define ZYNQMP_CSU_VCUDIS_VER_MASK ZYNQMP_CSU_VERSION_MASK & \
245 ~BIT(ZYNQMP_IPDIS_VCU_BIT)
246 #define MAX_VARIANTS_EV 3
248 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
249 !defined(CONFIG_SPL_BUILD)
250 static char *zynqmp_get_silicon_idcode_name(void)
254 static char name[ZYNQMP_VERSION_SIZE];
256 id = chip_id(IDCODE);
257 ver = chip_id(IDCODE2);
259 for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
260 if (zynqmp_devices[i].id == id) {
261 if (zynqmp_devices[i].evexists &&
262 !(ver & ZYNQMP_PL_STATUS_MASK))
264 if (zynqmp_devices[i].ver == (ver &
265 ZYNQMP_CSU_VERSION_MASK))
270 if (i >= ARRAY_SIZE(zynqmp_devices))
273 strncat(name, "zu", 2);
274 if (!zynqmp_devices[i].evexists ||
275 (ver & ZYNQMP_PL_STATUS_MASK)) {
276 strncat(name, zynqmp_devices[i].name,
277 ZYNQMP_VERSION_SIZE - 3);
282 * Here we are means, PL not powered up and ev variant
283 * exists. So, we need to ignore VCU disable bit(8) in
284 * version and findout if its CG or EG/EV variant.
286 for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
287 if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
288 (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
289 strncat(name, zynqmp_devices[i].name,
290 ZYNQMP_VERSION_SIZE - 3);
295 if (j >= MAX_VARIANTS_EV)
298 if (strstr(name, "eg") || strstr(name, "ev")) {
299 buf = strstr(name, "e");
307 int board_early_init_f(void)
310 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
313 pm_api_version = zynqmp_pmufw_version();
314 printf("PMUFW:\tv%d.%d\n",
315 pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
316 pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK);
318 if (pm_api_version < ZYNQMP_PM_VERSION)
319 panic("PMUFW version error. Expected: v%d.%d\n",
320 ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
323 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
332 #if defined(CONFIG_SPL_BUILD)
333 /* Check *at build time* if the filename is an non-empty string */
334 if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
335 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
336 zynqmp_pm_cfg_obj_size);
339 printf("EL Level:\tEL%d\n", current_el());
341 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
342 !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
343 defined(CONFIG_SPL_BUILD))
344 if (current_el() != 3) {
345 zynqmppl.name = zynqmp_get_silicon_idcode_name();
346 printf("Chip ID:\t%s\n", zynqmppl.name);
348 fpga_add(fpga_xilinx, &zynqmppl);
355 int board_early_init_r(void)
359 if (current_el() != 3)
362 val = readl(&crlapb_base->timestamp_ref_ctrl);
363 val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
366 val = readl(&crlapb_base->timestamp_ref_ctrl);
367 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
368 writel(val, &crlapb_base->timestamp_ref_ctrl);
370 /* Program freq register in System counter */
371 writel(zynqmp_get_system_timer_freq(),
372 &iou_scntr_secure->base_frequency_id_register);
373 /* And enable system counter */
374 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
375 &iou_scntr_secure->counter_control_register);
380 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
385 if (current_el() > 1) {
388 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
391 printf("FAIL: current EL is not above EL1\n");
397 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
398 int dram_init_banksize(void)
402 ret = fdtdec_setup_memory_banksize();
413 if (fdtdec_setup_mem_size_base() != 0)
419 int dram_init_banksize(void)
421 #if defined(CONFIG_NR_DRAM_BANKS)
422 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
423 gd->bd->bi_dram[0].size = get_effective_memsize();
433 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
434 CONFIG_SYS_SDRAM_SIZE);
440 void reset_cpu(ulong addr)
444 #if defined(CONFIG_BOARD_LATE_INIT)
445 static const struct {
448 } reset_reasons[] = {
449 { RESET_REASON_DEBUG_SYS, "DEBUG" },
450 { RESET_REASON_SOFT, "SOFT" },
451 { RESET_REASON_SRST, "SRST" },
452 { RESET_REASON_PSONLY, "PS-ONLY" },
453 { RESET_REASON_PMU, "PMU" },
454 { RESET_REASON_INTERNAL, "INTERNAL" },
455 { RESET_REASON_EXTERNAL, "EXTERNAL" },
459 static int reset_reason(void)
463 const char *reason = NULL;
465 ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, ®);
469 puts("Reset reason:\t");
471 for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
472 if (reg & reset_reasons[i].bit) {
473 reason = reset_reasons[i].name;
474 printf("%s ", reset_reasons[i].name);
481 env_set("reset_reason", reason);
483 ret = zynqmp_mmio_write(~0, ~0, (ulong)&crlapb_base->reset_reason);
490 static int set_fdtfile(void)
492 char *compatible, *fdtfile;
493 const char *suffix = ".dtb";
494 const char *vendor = "xilinx/";
496 if (env_get("fdtfile"))
499 compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
501 debug("Compatible: %s\n", compatible);
503 /* Discard vendor prefix */
504 strsep(&compatible, ",");
506 fdtfile = calloc(1, strlen(vendor) + strlen(compatible) +
511 sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix);
513 env_set("fdtfile", fdtfile);
520 int board_late_init(void)
527 int env_targets_len = 0;
533 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
537 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
538 debug("Saved variables - Skipping\n");
546 ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®);
550 if (reg >> BOOT_MODE_ALT_SHIFT)
551 reg >>= BOOT_MODE_ALT_SHIFT;
553 bootmode = reg & BOOT_MODES_MASK;
560 env_set("modeboot", "usb_dfu_spl");
565 env_set("modeboot", "jtagboot");
567 case QSPI_MODE_24BIT:
568 case QSPI_MODE_32BIT:
571 env_set("modeboot", "qspiboot");
576 env_set("modeboot", "emmcboot");
580 if (uclass_get_device_by_name(UCLASS_MMC,
581 "mmc@ff160000", &dev) &&
582 uclass_get_device_by_name(UCLASS_MMC,
583 "sdhci@ff160000", &dev)) {
584 puts("Boot from SD0 but without SD0 enabled!\n");
587 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
591 env_set("modeboot", "sdboot");
598 if (uclass_get_device_by_name(UCLASS_MMC,
599 "mmc@ff170000", &dev) &&
600 uclass_get_device_by_name(UCLASS_MMC,
601 "sdhci@ff170000", &dev)) {
602 puts("Boot from SD1 but without SD1 enabled!\n");
605 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
609 env_set("modeboot", "sdboot");
614 env_set("modeboot", "nandboot");
618 printf("Invalid Boot Mode:0x%x\n", bootmode);
623 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
624 debug("Bootseq len: %x\n", bootseq_len);
628 * One terminating char + one byte for space between mode
629 * and default boot_targets
631 env_targets = env_get("boot_targets");
633 env_targets_len = strlen(env_targets);
635 new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
641 sprintf(new_targets, "%s%x %s", mode, bootseq,
642 env_targets ? env_targets : "");
644 sprintf(new_targets, "%s %s", mode,
645 env_targets ? env_targets : "");
647 env_set("boot_targets", new_targets);
657 puts("Board: Xilinx ZynqMP\n");