board/xilinx/zynqmp/zynqmp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <debug_uart.h>
  10 #include <env.h>
  11 #include <init.h>
  12 #include <sata.h>
  13 #include <ahci.h>
  14 #include <scsi.h>
  15 #include <malloc.h>
  16 #include <wdt.h>
  17 #include <asm/arch/clk.h>
  18 #include <asm/arch/hardware.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/arch/psu_init_gpl.h>
  21 #include <asm/io.h>
  22 #include <dm/device.h>
  23 #include <dm/uclass.h>
  24 #include <usb.h>
  25 #include <dwc3-uboot.h>
  26 #include <zynqmppl.h>
  27 #include <zynqmp_firmware.h>
  28 #include <g_dnl.h>
  29 #include <linux/sizes.h>
  30
  31 #include "pm_cfg_obj.h"
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  36     !defined(CONFIG_SPL_BUILD)
  37 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  38
  39 static const struct {
  40         u32 id;
  41         u32 ver;
  42         char *name;
  43         bool evexists;
  44 } zynqmp_devices[] = {
  45         {
  46                 .id = 0x10,
  47                 .name = "3eg",
  48         },
  49         {
  50                 .id = 0x10,
  51                 .ver = 0x2c,
  52                 .name = "3cg",
  53         },
  54         {
  55                 .id = 0x11,
  56                 .name = "2eg",
  57         },
  58         {
  59                 .id = 0x11,
  60                 .ver = 0x2c,
  61                 .name = "2cg",
  62         },
  63         {
  64                 .id = 0x20,
  65                 .name = "5ev",
  66                 .evexists = 1,
  67         },
  68         {
  69                 .id = 0x20,
  70                 .ver = 0x100,
  71                 .name = "5eg",
  72                 .evexists = 1,
  73         },
  74         {
  75                 .id = 0x20,
  76                 .ver = 0x12c,
  77                 .name = "5cg",
  78                 .evexists = 1,
  79         },
  80         {
  81                 .id = 0x21,
  82                 .name = "4ev",
  83                 .evexists = 1,
  84         },
  85         {
  86                 .id = 0x21,
  87                 .ver = 0x100,
  88                 .name = "4eg",
  89                 .evexists = 1,
  90         },
  91         {
  92                 .id = 0x21,
  93                 .ver = 0x12c,
  94                 .name = "4cg",
  95                 .evexists = 1,
  96         },
  97         {
  98                 .id = 0x30,
  99                 .name = "7ev",
 100                 .evexists = 1,
 101         },
 102         {
 103                 .id = 0x30,
 104                 .ver = 0x100,
 105                 .name = "7eg",
 106                 .evexists = 1,
 107         },
 108         {
 109                 .id = 0x30,
 110                 .ver = 0x12c,
 111                 .name = "7cg",
 112                 .evexists = 1,
 113         },
 114         {
 115                 .id = 0x38,
 116                 .name = "9eg",
 117         },
 118         {
 119                 .id = 0x38,
 120                 .ver = 0x2c,
 121                 .name = "9cg",
 122         },
 123         {
 124                 .id = 0x39,
 125                 .name = "6eg",
 126         },
 127         {
 128                 .id = 0x39,
 129                 .ver = 0x2c,
 130                 .name = "6cg",
 131         },
 132         {
 133                 .id = 0x40,
 134                 .name = "11eg",
 135         },
 136         { /* For testing purpose only */
 137                 .id = 0x50,
 138                 .ver = 0x2c,
 139                 .name = "15cg",
 140         },
 141         {
 142                 .id = 0x50,
 143                 .name = "15eg",
 144         },
 145         {
 146                 .id = 0x58,
 147                 .name = "19eg",
 148         },
 149         {
 150                 .id = 0x59,
 151                 .name = "17eg",
 152         },
 153         {
 154                 .id = 0x61,
 155                 .name = "21dr",
 156         },
 157         {
 158                 .id = 0x63,
 159                 .name = "23dr",
 160         },
 161         {
 162                 .id = 0x65,
 163                 .name = "25dr",
 164         },
 165         {
 166                 .id = 0x64,
 167                 .name = "27dr",
 168         },
 169         {
 170                 .id = 0x60,
 171                 .name = "28dr",
 172         },
 173         {
 174                 .id = 0x62,
 175                 .name = "29dr",
 176         },
 177         {
 178                 .id = 0x66,
 179                 .name = "39dr",
 180         },
 181         {
 182                 .id = 0x7b,
 183                 .name = "48dr",
 184         },
 185         {
 186                 .id = 0x7e,
 187                 .name = "49dr",
 188         },
 189 };
 190 #endif
 191
 192 int chip_id(unsigned char id)
 193 {
 194         struct pt_regs regs;
 195         int val = -EINVAL;
 196
 197         if (current_el() != 3) {
 198                 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
 199                 regs.regs[1] = 0;
 200                 regs.regs[2] = 0;
 201                 regs.regs[3] = 0;
 202
 203                 smc_call(&regs);
 204
 205                 /*
 206                  * SMC returns:
 207                  * regs[0][31:0]  = status of the operation
 208                  * regs[0][63:32] = CSU.IDCODE register
 209                  * regs[1][31:0]  = CSU.version register
 210                  * regs[1][63:32] = CSU.IDCODE2 register
 211                  */
 212                 switch (id) {
 213                 case IDCODE:
 214                         regs.regs[0] = upper_32_bits(regs.regs[0]);
 215                         regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 216                                         ZYNQMP_CSU_IDCODE_SVD_MASK;
 217                         regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 218                         val = regs.regs[0];
 219                         break;
 220                 case VERSION:
 221                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 222                         regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
 223                         val = regs.regs[1];
 224                         break;
 225                 case IDCODE2:
 226                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 227                         regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
 228                         val = regs.regs[1];
 229                         break;
 230                 default:
 231                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 232                 }
 233         } else {
 234                 switch (id) {
 235                 case IDCODE:
 236                         val = readl(ZYNQMP_CSU_IDCODE_ADDR);
 237                         val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 238                                ZYNQMP_CSU_IDCODE_SVD_MASK;
 239                         val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 240                         break;
 241                 case VERSION:
 242                         val = readl(ZYNQMP_CSU_VER_ADDR);
 243                         val &= ZYNQMP_CSU_SILICON_VER_MASK;
 244                         break;
 245                 default:
 246                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 247                 }
 248         }
 249
 250         return val;
 251 }
 252
 253 #define ZYNQMP_VERSION_SIZE             9
 254 #define ZYNQMP_PL_STATUS_BIT            9
 255 #define ZYNQMP_IPDIS_VCU_BIT            8
 256 #define ZYNQMP_PL_STATUS_MASK           BIT(ZYNQMP_PL_STATUS_BIT)
 257 #define ZYNQMP_CSU_VERSION_MASK         ~(ZYNQMP_PL_STATUS_MASK)
 258 #define ZYNQMP_CSU_VCUDIS_VER_MASK      ZYNQMP_CSU_VERSION_MASK & \
 259                                         ~BIT(ZYNQMP_IPDIS_VCU_BIT)
 260 #define MAX_VARIANTS_EV                 3
 261
 262 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 263         !defined(CONFIG_SPL_BUILD)
 264 static char *zynqmp_get_silicon_idcode_name(void)
 265 {
 266         u32 i, id, ver, j;
 267         char *buf;
 268         static char name[ZYNQMP_VERSION_SIZE];
 269
 270         id = chip_id(IDCODE);
 271         ver = chip_id(IDCODE2);
 272
 273         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 274                 if (zynqmp_devices[i].id == id) {
 275                         if (zynqmp_devices[i].evexists &&
 276                             !(ver & ZYNQMP_PL_STATUS_MASK))
 277                                 break;
 278                         if (zynqmp_devices[i].ver == (ver &
 279                             ZYNQMP_CSU_VERSION_MASK))
 280                                 break;
 281                 }
 282         }
 283
 284         if (i >= ARRAY_SIZE(zynqmp_devices))
 285                 return "unknown";
 286
 287         strncat(name, "zu", 2);
 288         if (!zynqmp_devices[i].evexists ||
 289             (ver & ZYNQMP_PL_STATUS_MASK)) {
 290                 strncat(name, zynqmp_devices[i].name,
 291                         ZYNQMP_VERSION_SIZE - 3);
 292                 return name;
 293         }
 294
 295         /*
 296          * Here we are means, PL not powered up and ev variant
 297          * exists. So, we need to ignore VCU disable bit(8) in
 298          * version and findout if its CG or EG/EV variant.
 299          */
 300         for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
 301                 if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
 302                     (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
 303                         strncat(name, zynqmp_devices[i].name,
 304                                 ZYNQMP_VERSION_SIZE - 3);
 305                         break;
 306                 }
 307         }
 308
 309         if (j >= MAX_VARIANTS_EV)
 310                 return "unknown";
 311
 312         if (strstr(name, "eg") || strstr(name, "ev")) {
 313                 buf = strstr(name, "e");
 314                 *buf = '\0';
 315         }
 316
 317         return name;
 318 }
 319 #endif
 320
 321 int board_early_init_f(void)
 322 {
 323 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 324         int ret;
 325
 326         ret = psu_init();
 327         if (ret)
 328                 return ret;
 329 #endif
 330
 331 #ifdef CONFIG_DEBUG_UART
 332         /* Uart debug for sure */
 333         debug_uart_init();
 334         puts("Debug uart enabled\n"); /* or printch() */
 335 #endif
 336
 337         return 0;
 338 }
 339
 340 static int multi_boot(void)
 341 {
 342         u32 multiboot;
 343
 344         multiboot = readl(&csu_base->multi_boot);
 345
 346         printf("Multiboot:\t%x\n", multiboot);
 347
 348         return 0;
 349 }
 350
 351 int board_init(void)
 352 {
 353 #if defined(CONFIG_ZYNQMP_FIRMWARE)
 354         struct udevice *dev;
 355
 356         uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
 357         if (!dev)
 358                 panic("PMU Firmware device not found - Enable it");
 359 #endif
 360
 361 #if defined(CONFIG_SPL_BUILD)
 362         /* Check *at build time* if the filename is an non-empty string */
 363         if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
 364                 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
 365                                                 zynqmp_pm_cfg_obj_size);
 366 #endif
 367
 368         printf("EL Level:\tEL%d\n", current_el());
 369
 370 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 371     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
 372     defined(CONFIG_SPL_BUILD))
 373         if (current_el() != 3) {
 374                 zynqmppl.name = zynqmp_get_silicon_idcode_name();
 375                 printf("Chip ID:\t%s\n", zynqmppl.name);
 376                 fpga_init();
 377                 fpga_add(fpga_xilinx, &zynqmppl);
 378         }
 379 #endif
 380
 381         if (current_el() == 3)
 382                 multi_boot();
 383
 384         return 0;
 385 }
 386
 387 int board_early_init_r(void)
 388 {
 389         u32 val;
 390
 391         if (current_el() != 3)
 392                 return 0;
 393
 394         val = readl(&crlapb_base->timestamp_ref_ctrl);
 395         val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 396
 397         if (!val) {
 398                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 399                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 400                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 401
 402                 /* Program freq register in System counter */
 403                 writel(zynqmp_get_system_timer_freq(),
 404                        &iou_scntr_secure->base_frequency_id_register);
 405                 /* And enable system counter */
 406                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 407                        &iou_scntr_secure->counter_control_register);
 408         }
 409         return 0;
 410 }
 411
 412 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
 413                          char * const argv[])
 414 {
 415         int ret = 0;
 416
 417         if (current_el() > 1) {
 418                 smp_kick_all_cpus();
 419                 dcache_disable();
 420                 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
 421                                     ES_TO_AARCH64);
 422         } else {
 423                 printf("FAIL: current EL is not above EL1\n");
 424                 ret = EINVAL;
 425         }
 426         return ret;
 427 }
 428
 429 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 430 int dram_init_banksize(void)
 431 {
 432         int ret;
 433
 434         ret = fdtdec_setup_memory_banksize();
 435         if (ret)
 436                 return ret;
 437
 438         mem_map_fill();
 439
 440         return 0;
 441 }
 442
 443 int dram_init(void)
 444 {
 445         if (fdtdec_setup_mem_size_base() != 0)
 446                 return -EINVAL;
 447
 448         return 0;
 449 }
 450 #else
 451 int dram_init_banksize(void)
 452 {
 453 #if defined(CONFIG_NR_DRAM_BANKS)
 454         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 455         gd->bd->bi_dram[0].size = get_effective_memsize();
 456 #endif
 457
 458         mem_map_fill();
 459
 460         return 0;
 461 }
 462
 463 int dram_init(void)
 464 {
 465         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 466                                     CONFIG_SYS_SDRAM_SIZE);
 467
 468         return 0;
 469 }
 470 #endif
 471
 472 void reset_cpu(ulong addr)
 473 {
 474 }
 475
 476 #if defined(CONFIG_BOARD_LATE_INIT)
 477 static const struct {
 478         u32 bit;
 479         const char *name;
 480 } reset_reasons[] = {
 481         { RESET_REASON_DEBUG_SYS, "DEBUG" },
 482         { RESET_REASON_SOFT, "SOFT" },
 483         { RESET_REASON_SRST, "SRST" },
 484         { RESET_REASON_PSONLY, "PS-ONLY" },
 485         { RESET_REASON_PMU, "PMU" },
 486         { RESET_REASON_INTERNAL, "INTERNAL" },
 487         { RESET_REASON_EXTERNAL, "EXTERNAL" },
 488         {}
 489 };
 490
 491 static int reset_reason(void)
 492 {
 493         u32 reg;
 494         int i, ret;
 495         const char *reason = NULL;
 496
 497         ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
 498         if (ret)
 499                 return -EINVAL;
 500
 501         puts("Reset reason:\t");
 502
 503         for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
 504                 if (reg & reset_reasons[i].bit) {
 505                         reason = reset_reasons[i].name;
 506                         printf("%s ", reset_reasons[i].name);
 507                         break;
 508                 }
 509         }
 510
 511         puts("\n");
 512
 513         env_set("reset_reason", reason);
 514
 515         ret = zynqmp_mmio_write(~0, ~0, (ulong)&crlapb_base->reset_reason);
 516         if (ret)
 517                 return -EINVAL;
 518
 519         return ret;
 520 }
 521
 522 static int set_fdtfile(void)
 523 {
 524         char *compatible, *fdtfile;
 525         const char *suffix = ".dtb";
 526         const char *vendor = "xilinx/";
 527
 528         if (env_get("fdtfile"))
 529                 return 0;
 530
 531         compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
 532         if (compatible) {
 533                 debug("Compatible: %s\n", compatible);
 534
 535                 /* Discard vendor prefix */
 536                 strsep(&compatible, ",");
 537
 538                 fdtfile = calloc(1, strlen(vendor) + strlen(compatible) +
 539                                  strlen(suffix) + 1);
 540                 if (!fdtfile)
 541                         return -ENOMEM;
 542
 543                 sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix);
 544
 545                 env_set("fdtfile", fdtfile);
 546                 free(fdtfile);
 547         }
 548
 549         return 0;
 550 }
 551
 552 int board_late_init(void)
 553 {
 554         u32 reg = 0;
 555         u8 bootmode;
 556         struct udevice *dev;
 557         int bootseq = -1;
 558         int bootseq_len = 0;
 559         int env_targets_len = 0;
 560         const char *mode;
 561         char *new_targets;
 562         char *env_targets;
 563         int ret;
 564         ulong initrd_hi;
 565
 566 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
 567         usb_ether_init();
 568 #endif
 569
 570         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 571                 debug("Saved variables - Skipping\n");
 572                 return 0;
 573         }
 574
 575         ret = set_fdtfile();
 576         if (ret)
 577                 return ret;
 578
 579         ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
 580         if (ret)
 581                 return -EINVAL;
 582
 583         if (reg >> BOOT_MODE_ALT_SHIFT)
 584                 reg >>= BOOT_MODE_ALT_SHIFT;
 585
 586         bootmode = reg & BOOT_MODES_MASK;
 587
 588         puts("Bootmode: ");
 589         switch (bootmode) {
 590         case USB_MODE:
 591                 puts("USB_MODE\n");
 592                 mode = "usb";
 593                 env_set("modeboot", "usb_dfu_spl");
 594                 break;
 595         case JTAG_MODE:
 596                 puts("JTAG_MODE\n");
 597                 mode = "jtag pxe dhcp";
 598                 env_set("modeboot", "jtagboot");
 599                 break;
 600         case QSPI_MODE_24BIT:
 601         case QSPI_MODE_32BIT:
 602                 mode = "qspi0";
 603                 puts("QSPI_MODE\n");
 604                 env_set("modeboot", "qspiboot");
 605                 break;
 606         case EMMC_MODE:
 607                 puts("EMMC_MODE\n");
 608                 if (uclass_get_device_by_name(UCLASS_MMC,
 609                                               "mmc@ff160000", &dev) &&
 610                     uclass_get_device_by_name(UCLASS_MMC,
 611                                               "sdhci@ff160000", &dev)) {
 612                         puts("Boot from EMMC but without SD0 enabled!\n");
 613                         return -1;
 614                 }
 615                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 616
 617                 mode = "mmc";
 618                 bootseq = dev->seq;
 619                 break;
 620         case SD_MODE:
 621                 puts("SD_MODE\n");
 622                 if (uclass_get_device_by_name(UCLASS_MMC,
 623                                               "mmc@ff160000", &dev) &&
 624                     uclass_get_device_by_name(UCLASS_MMC,
 625                                               "sdhci@ff160000", &dev)) {
 626                         puts("Boot from SD0 but without SD0 enabled!\n");
 627                         return -1;
 628                 }
 629                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 630
 631                 mode = "mmc";
 632                 bootseq = dev->seq;
 633                 env_set("modeboot", "sdboot");
 634                 break;
 635         case SD1_LSHFT_MODE:
 636                 puts("LVL_SHFT_");
 637                 /* fall through */
 638         case SD_MODE1:
 639                 puts("SD_MODE1\n");
 640                 if (uclass_get_device_by_name(UCLASS_MMC,
 641                                               "mmc@ff170000", &dev) &&
 642                     uclass_get_device_by_name(UCLASS_MMC,
 643                                               "sdhci@ff170000", &dev)) {
 644                         puts("Boot from SD1 but without SD1 enabled!\n");
 645                         return -1;
 646                 }
 647                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 648
 649                 mode = "mmc";
 650                 bootseq = dev->seq;
 651                 env_set("modeboot", "sdboot");
 652                 break;
 653         case NAND_MODE:
 654                 puts("NAND_MODE\n");
 655                 mode = "nand0";
 656                 env_set("modeboot", "nandboot");
 657                 break;
 658         default:
 659                 mode = "";
 660                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 661                 break;
 662         }
 663
 664         if (bootseq >= 0) {
 665                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 666                 debug("Bootseq len: %x\n", bootseq_len);
 667         }
 668
 669         /*
 670          * One terminating char + one byte for space between mode
 671          * and default boot_targets
 672          */
 673         env_targets = env_get("boot_targets");
 674         if (env_targets)
 675                 env_targets_len = strlen(env_targets);
 676
 677         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 678                              bootseq_len);
 679         if (!new_targets)
 680                 return -ENOMEM;
 681
 682         if (bootseq >= 0)
 683                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 684                         env_targets ? env_targets : "");
 685         else
 686                 sprintf(new_targets, "%s %s", mode,
 687                         env_targets ? env_targets : "");
 688
 689         env_set("boot_targets", new_targets);
 690
 691         initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
 692         initrd_hi = round_down(initrd_hi, SZ_16M);
 693         env_set_addr("initrd_high", (void *)initrd_hi);
 694
 695         env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
 696
 697         reset_reason();
 698
 699         return 0;
 700 }
 701 #endif
 702
 703 int checkboard(void)
 704 {
 705         puts("Board: Xilinx ZynqMP\n");
 706         return 0;
 707 }