1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx ZynqMP SoC Tap Delay Programming
5 * Copyright (C) 2018 Xilinx, Inc.
9 #include <asm/arch/sys_proto.h>
11 #define SD_DLL_CTRL 0xFF180358
12 #define SD_ITAP_DLY 0xFF180314
13 #define SD_OTAP_DLY 0xFF180318
14 #define SD0_DLL_RST_MASK 0x00000004
15 #define SD0_DLL_RST 0x00000004
16 #define SD1_DLL_RST_MASK 0x00040000
17 #define SD1_DLL_RST 0x00040000
18 #define SD0_ITAPCHGWIN_MASK 0x00000200
19 #define SD0_ITAPCHGWIN 0x00000200
20 #define SD1_ITAPCHGWIN_MASK 0x02000000
21 #define SD1_ITAPCHGWIN 0x02000000
22 #define SD0_ITAPDLYENA_MASK 0x00000100
23 #define SD0_ITAPDLYENA 0x00000100
24 #define SD1_ITAPDLYENA_MASK 0x01000000
25 #define SD1_ITAPDLYENA 0x01000000
26 #define SD0_ITAPDLYSEL_MASK 0x000000FF
27 #define SD0_ITAPDLYSEL_HSD 0x00000015
28 #define SD0_ITAPDLYSEL_SD_DDR50 0x0000003D
29 #define SD0_ITAPDLYSEL_MMC_DDR50 0x00000012
31 #define SD1_ITAPDLYSEL_MASK 0x00FF0000
32 #define SD1_ITAPDLYSEL_HSD 0x00150000
33 #define SD1_ITAPDLYSEL_SD_DDR50 0x003D0000
34 #define SD1_ITAPDLYSEL_MMC_DDR50 0x00120000
36 #define SD0_OTAPDLYSEL_MASK 0x0000003F
37 #define SD0_OTAPDLYSEL_MMC_HSD 0x00000006
38 #define SD0_OTAPDLYSEL_SD_HSD 0x00000005
39 #define SD0_OTAPDLYSEL_SDR50 0x00000003
40 #define SD0_OTAPDLYSEL_SDR104_B0 0x00000003
41 #define SD0_OTAPDLYSEL_SDR104_B2 0x00000002
42 #define SD0_OTAPDLYSEL_SD_DDR50 0x00000004
43 #define SD0_OTAPDLYSEL_MMC_DDR50 0x00000006
45 #define SD1_OTAPDLYSEL_MASK 0x003F0000
46 #define SD1_OTAPDLYSEL_MMC_HSD 0x00060000
47 #define SD1_OTAPDLYSEL_SD_HSD 0x00050000
48 #define SD1_OTAPDLYSEL_SDR50 0x00030000
49 #define SD1_OTAPDLYSEL_SDR104_B0 0x00030000
50 #define SD1_OTAPDLYSEL_SDR104_B2 0x00020000
51 #define SD1_OTAPDLYSEL_SD_DDR50 0x00040000
52 #define SD1_OTAPDLYSEL_MMC_DDR50 0x00060000
56 #define MMC_TIMING_UHS_SDR25 1
57 #define MMC_TIMING_UHS_SDR50 2
58 #define MMC_TIMING_UHS_SDR104 3
59 #define MMC_TIMING_UHS_DDR50 4
60 #define MMC_TIMING_MMC_HS200 5
61 #define MMC_TIMING_SD_HS 6
62 #define MMC_TIMING_MMC_DDR52 7
63 #define MMC_TIMING_MMC_HS 8
65 void zynqmp_dll_reset(u8 deviceid)
69 zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK,
72 zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
77 /* Release DLL Reset */
79 zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
81 zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
84 static void arasan_zynqmp_tap_sdr104(u8 deviceid, u8 timing, u8 bank)
88 if (bank == MMC_BANK2)
89 zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
90 SD0_OTAPDLYSEL_SDR104_B2);
92 zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
93 SD0_OTAPDLYSEL_SDR104_B0);
96 if (bank == MMC_BANK2)
97 zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
98 SD1_OTAPDLYSEL_SDR104_B2);
100 zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
101 SD1_OTAPDLYSEL_SDR104_B0);
105 static void arasan_zynqmp_tap_hs(u8 deviceid, u8 timing, u8 bank)
109 zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
111 zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
113 zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
115 zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, 0x0);
117 if (timing == MMC_TIMING_MMC_HS)
118 zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
119 SD0_OTAPDLYSEL_MMC_HSD);
121 zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
122 SD0_OTAPDLYSEL_SD_HSD);
125 zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
127 zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
129 zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
131 zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, 0x0);
133 if (timing == MMC_TIMING_MMC_HS)
134 zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
135 SD1_OTAPDLYSEL_MMC_HSD);
137 zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
138 SD1_OTAPDLYSEL_SD_HSD);
142 static void arasan_zynqmp_tap_ddr50(u8 deviceid, u8 timing, u8 bank)
146 zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
148 zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
150 if (timing == MMC_TIMING_UHS_DDR50)
151 zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
152 SD0_ITAPDLYSEL_SD_DDR50);
154 zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
155 SD0_ITAPDLYSEL_MMC_DDR50);
156 zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, 0x0);
158 if (timing == MMC_TIMING_UHS_DDR50)
159 zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
160 SD0_OTAPDLYSEL_SD_DDR50);
162 zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
163 SD0_OTAPDLYSEL_MMC_DDR50);
166 zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
168 zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
170 if (timing == MMC_TIMING_UHS_DDR50)
171 zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
172 SD1_ITAPDLYSEL_SD_DDR50);
174 zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
175 SD1_ITAPDLYSEL_MMC_DDR50);
176 zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, 0x0);
178 if (timing == MMC_TIMING_UHS_DDR50)
179 zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
180 SD1_OTAPDLYSEL_SD_DDR50);
182 zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
183 SD1_OTAPDLYSEL_MMC_DDR50);
187 static void arasan_zynqmp_tap_sdr50(u8 deviceid, u8 timing, u8 bank)
191 zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
192 SD0_OTAPDLYSEL_SDR50);
195 zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
196 SD1_OTAPDLYSEL_SDR50);
200 void arasan_zynqmp_set_tapdelay(u8 deviceid, u8 timing, u8 bank)
203 zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK,
206 zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
210 case MMC_TIMING_UHS_SDR25:
211 arasan_zynqmp_tap_hs(deviceid, timing, bank);
213 case MMC_TIMING_UHS_SDR50:
214 arasan_zynqmp_tap_sdr50(deviceid, timing, bank);
216 case MMC_TIMING_UHS_SDR104:
217 case MMC_TIMING_MMC_HS200:
218 arasan_zynqmp_tap_sdr104(deviceid, timing, bank);
220 case MMC_TIMING_UHS_DDR50:
221 arasan_zynqmp_tap_ddr50(deviceid, timing, bank);
226 zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
228 zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);