1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
4 * (C) Copyright 2013 - 2018 Xilinx, Inc.
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/arch/ps7_init_gpl.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
21 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
22 static xilinx_desc fpga;
24 /* It can be done differently */
25 static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7);
26 static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
27 static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12);
28 static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14);
29 static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
30 static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
31 static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
32 static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
33 static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
34 static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
37 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
38 static struct udevice *watchdog_dev;
41 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F)
42 int board_early_init_f(void)
44 # if defined(CONFIG_WDT)
45 /* bss is not cleared at time when watchdog_reset() is called */
55 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
56 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
59 idcode = zynq_slcr_get_idcode();
62 case XILINX_ZYNQ_7007S:
65 case XILINX_ZYNQ_7010:
68 case XILINX_ZYNQ_7012S:
71 case XILINX_ZYNQ_7014S:
74 case XILINX_ZYNQ_7015:
77 case XILINX_ZYNQ_7020:
80 case XILINX_ZYNQ_7030:
83 case XILINX_ZYNQ_7035:
86 case XILINX_ZYNQ_7045:
89 case XILINX_ZYNQ_7100:
95 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
96 if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
97 puts("Watchdog: Not found!\n");
99 wdt_start(watchdog_dev, 0, 0);
100 puts("Watchdog: Started\n");
104 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
105 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
107 fpga_add(fpga_xilinx, &fpga);
113 int board_late_init(void)
115 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
117 env_set("modeboot", "qspiboot");
120 env_set("modeboot", "nandboot");
123 env_set("modeboot", "norboot");
126 env_set("modeboot", "sdboot");
129 env_set("modeboot", "jtagboot");
132 env_set("modeboot", "");
139 #ifdef CONFIG_DISPLAY_BOARDINFO
142 u32 version = zynq_get_silicon_version();
145 if (version > (PCW_SILICON_VERSION_3 << 1))
148 puts("Board: Xilinx Zynq\n");
149 printf("Silicon: v%d.%d\n", version >> 1, version & 1);
155 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
157 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
158 defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)
159 if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
160 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
162 printf("I2C EEPROM MAC address read failed\n");
168 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
169 int dram_init_banksize(void)
171 return fdtdec_setup_memory_banksize();
176 if (fdtdec_setup_memory_size() != 0)
186 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
187 CONFIG_SYS_SDRAM_SIZE);
195 #if defined(CONFIG_WATCHDOG)
196 /* Called by macro WATCHDOG_RESET */
197 void watchdog_reset(void)
199 # if !defined(CONFIG_SPL_BUILD)
200 static ulong next_reset;
206 now = timer_get_us();
208 /* Do not reset the watchdog too often */
209 if (now > next_reset) {
210 wdt_reset(watchdog_dev);
211 next_reset = now + 1000;