2 * (C) Copyright 2007 Michal Simek
4 * Michal SIMEK <monstr@monstr.eu>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * CAUTION: This file is automatically generated by libgen.
25 * Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
28 /* System Clock Frequency */
29 #define XILINX_CLOCK_FREQ 100000000
31 /* Interrupt controller is opb_intc_0 */
32 #define XILINX_INTC_BASEADDR 0x41200000
33 #define XILINX_INTC_NUM_INTR_INPUTS 11
35 /* Timer pheriphery is opb_timer_1 */
36 #define XILINX_TIMER_BASEADDR 0x41c00000
37 #define XILINX_TIMER_IRQ 1
39 /* Uart pheriphery is RS232_Uart_1 */
40 #define XILINX_UART_BASEADDR 0x40600000
41 #define XILINX_UART_BAUDRATE 115200
43 /* GPIO is LEDs_4Bit*/
44 #define XILINX_GPIO_BASEADDR 0x40000000
46 /* FLASH doesn't exist none */
48 /* Main Memory is DDR_256MB_32MX64_rank1_row13_col10_cl2_5 */
49 #define XILINX_RAM_START 0x30000000
50 #define XILINX_RAM_SIZE 0x10000000
52 /* Sysace Controller is SysACE_CompactFlash */
53 #define XILINX_SYSACE_BASEADDR 0x41800000
54 #define XILINX_SYSACE_HIGHADDR 0x4180ffff
55 #define XILINX_SYSACE_MEM_WIDTH 16
57 /* Ethernet controller is Ethernet_MAC */
58 #define XPAR_XEMAC_NUM_INSTANCES 1
59 #define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
60 #define XPAR_OPB_ETHERNET_0_BASEADDR 0x40c00000
61 #define XPAR_OPB_ETHERNET_0_HIGHADDR 0x40c0ffff
62 #define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
63 #define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
64 #define XPAR_OPB_ETHERNET_0_MII_EXIST 1