1 /*********************************************************************
3 # CAUTION: This file is automatically generated by libgen.
4 # Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
5 # Description: U-BOOT Configuration File
6 # Michal Simek - monstr@monstr.eu
8 **********************************************************************/
10 /* System Clock Frequency */
11 #define XILINX_CLOCK_FREQ 100000000
13 /* Interrupt controller is opb_intc_0 */
14 #define XILINX_INTC_BASEADDR 0x41200000
15 #define XILINX_INTC_NUM_INTR_INPUTS 11
17 /* Timer pheriphery is opb_timer_1 */
18 #define XILINX_TIMER_BASEADDR 0x41c00000
19 #define XILINX_TIMER_IRQ 1
21 /* Uart pheriphery is RS232_Uart_1 */
22 #define XILINX_UART_BASEADDR 0x40600000
23 #define XILINX_UART_BAUDRATE 115200
25 /* GPIO is LEDs_4Bit*/
26 #define XILINX_GPIO_BASEADDR 0x40000000
28 /* FLASH doesn't exist none */
30 /* Main Memory is DDR_256MB_32MX64_rank1_row13_col10_cl2_5 */
31 #define XILINX_RAM_START 0x30000000
32 #define XILINX_RAM_SIZE 0x10000000
34 /* Sysace Controller is SysACE_CompactFlash */
35 #define XILINX_SYSACE_BASEADDR 0x41800000
36 #define XILINX_SYSACE_HIGHADDR 0x4180ffff
37 #define XILINX_SYSACE_MEM_WIDTH 16
39 /* Ethernet controller is Ethernet_MAC */
40 #define XPAR_XEMAC_NUM_INSTANCES 1
41 #define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
42 #define XPAR_OPB_ETHERNET_0_BASEADDR 0x40c00000
43 #define XPAR_OPB_ETHERNET_0_HIGHADDR 0x40c0ffff
44 #define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
45 #define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
46 #define XPAR_OPB_ETHERNET_0_MII_EXIST 1