1 /******************************************************************************
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
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13 * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
14 * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
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19 * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
20 * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
21 * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
22 * FITNESS FOR A PARTICULAR PURPOSE.
25 * Xilinx hardware products are not intended for use in life support
26 * appliances, devices, or systems. Use in such applications is
27 * expressly prohibited.
30 * (c) Copyright 2002-2004 Xilinx Inc.
31 * All rights reserved.
34 * You should have received a copy of the GNU General Public License along
35 * with this program; if not, write to the Free Software Foundation, Inc.,
36 * 675 Mass Ave, Cambridge, MA 02139, USA.
38 ******************************************************************************/
39 /*****************************************************************************/
44 * This header file contains identifiers and low-level driver functions (or
45 * macros) that can be used to access the device. High-level driver functions
46 * are defined in xemac.h.
49 * MODIFICATION HISTORY:
51 * Ver Who Date Changes
52 * ----- ---- -------- -----------------------------------------------
53 * 1.00b rpm 04/26/02 First release
54 * 1.00b rmm 09/23/02 Added XEmac_mPhyReset macro
55 * 1.00c rpm 12/05/02 New version includes support for simple DMA
58 ******************************************************************************/
60 #ifndef XEMAC_L_H /* prevent circular inclusions */
61 #define XEMAC_L_H /* by using protection macros */
63 /***************************** Include Files *********************************/
65 #include "xbasic_types.h"
68 /************************** Constant Definitions *****************************/
70 /* Offset of the MAC registers from the IPIF base address */
71 #define XEM_REG_OFFSET 0x1100UL
74 * Register offsets for the Ethernet MAC. Each register is 32 bits.
76 #define XEM_EMIR_OFFSET (XEM_REG_OFFSET + 0x0) /* EMAC Module ID */
77 #define XEM_ECR_OFFSET (XEM_REG_OFFSET + 0x4) /* MAC Control */
78 #define XEM_IFGP_OFFSET (XEM_REG_OFFSET + 0x8) /* Interframe Gap */
79 #define XEM_SAH_OFFSET (XEM_REG_OFFSET + 0xC) /* Station addr, high */
80 #define XEM_SAL_OFFSET (XEM_REG_OFFSET + 0x10) /* Station addr, low */
81 #define XEM_MGTCR_OFFSET (XEM_REG_OFFSET + 0x14) /* MII mgmt control */
82 #define XEM_MGTDR_OFFSET (XEM_REG_OFFSET + 0x18) /* MII mgmt data */
83 #define XEM_RPLR_OFFSET (XEM_REG_OFFSET + 0x1C) /* Rx packet length */
84 #define XEM_TPLR_OFFSET (XEM_REG_OFFSET + 0x20) /* Tx packet length */
85 #define XEM_TSR_OFFSET (XEM_REG_OFFSET + 0x24) /* Tx status */
86 #define XEM_RMFC_OFFSET (XEM_REG_OFFSET + 0x28) /* Rx missed frames */
87 #define XEM_RCC_OFFSET (XEM_REG_OFFSET + 0x2C) /* Rx collisions */
88 #define XEM_RFCSEC_OFFSET (XEM_REG_OFFSET + 0x30) /* Rx FCS errors */
89 #define XEM_RAEC_OFFSET (XEM_REG_OFFSET + 0x34) /* Rx alignment errors */
90 #define XEM_TEDC_OFFSET (XEM_REG_OFFSET + 0x38) /* Transmit excess
94 * Register offsets for the IPIF components
96 #define XEM_ISR_OFFSET 0x20UL /* Interrupt status */
98 #define XEM_DMA_OFFSET 0x2300UL
99 #define XEM_DMA_SEND_OFFSET (XEM_DMA_OFFSET + 0x0) /* DMA send channel */
100 #define XEM_DMA_RECV_OFFSET (XEM_DMA_OFFSET + 0x40) /* DMA recv channel */
102 #define XEM_PFIFO_OFFSET 0x2000UL
103 #define XEM_PFIFO_TXREG_OFFSET (XEM_PFIFO_OFFSET + 0x0) /* Tx registers */
104 #define XEM_PFIFO_RXREG_OFFSET (XEM_PFIFO_OFFSET + 0x10) /* Rx registers */
105 #define XEM_PFIFO_TXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x100) /* Tx keyhole */
106 #define XEM_PFIFO_RXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x200) /* Rx keyhole */
109 * EMAC Module Identification Register (EMIR)
111 #define XEM_EMIR_VERSION_MASK 0xFFFF0000UL /* Device version */
112 #define XEM_EMIR_TYPE_MASK 0x0000FF00UL /* Device type */
115 * EMAC Control Register (ECR)
117 #define XEM_ECR_FULL_DUPLEX_MASK 0x80000000UL /* Full duplex mode */
118 #define XEM_ECR_XMIT_RESET_MASK 0x40000000UL /* Reset transmitter */
119 #define XEM_ECR_XMIT_ENABLE_MASK 0x20000000UL /* Enable transmitter */
120 #define XEM_ECR_RECV_RESET_MASK 0x10000000UL /* Reset receiver */
121 #define XEM_ECR_RECV_ENABLE_MASK 0x08000000UL /* Enable receiver */
122 #define XEM_ECR_PHY_ENABLE_MASK 0x04000000UL /* Enable PHY */
123 #define XEM_ECR_XMIT_PAD_ENABLE_MASK 0x02000000UL /* Enable xmit pad insert */
124 #define XEM_ECR_XMIT_FCS_ENABLE_MASK 0x01000000UL /* Enable xmit FCS insert */
125 #define XEM_ECR_XMIT_ADDR_INSERT_MASK 0x00800000UL /* Enable xmit source addr
127 #define XEM_ECR_XMIT_ERROR_INSERT_MASK 0x00400000UL /* Insert xmit error */
128 #define XEM_ECR_XMIT_ADDR_OVWRT_MASK 0x00200000UL /* Enable xmit source addr
130 #define XEM_ECR_LOOPBACK_MASK 0x00100000UL /* Enable internal
132 #define XEM_ECR_RECV_STRIP_ENABLE_MASK 0x00080000UL /* Enable recv pad/fcs strip */
133 #define XEM_ECR_UNICAST_ENABLE_MASK 0x00020000UL /* Enable unicast addr */
134 #define XEM_ECR_MULTI_ENABLE_MASK 0x00010000UL /* Enable multicast addr */
135 #define XEM_ECR_BROAD_ENABLE_MASK 0x00008000UL /* Enable broadcast addr */
136 #define XEM_ECR_PROMISC_ENABLE_MASK 0x00004000UL /* Enable promiscuous mode */
137 #define XEM_ECR_RECV_ALL_MASK 0x00002000UL /* Receive all frames */
138 #define XEM_ECR_RESERVED2_MASK 0x00001000UL /* Reserved */
139 #define XEM_ECR_MULTI_HASH_ENABLE_MASK 0x00000800UL /* Enable multicast hash */
140 #define XEM_ECR_PAUSE_FRAME_MASK 0x00000400UL /* Interpret pause frames */
141 #define XEM_ECR_CLEAR_HASH_MASK 0x00000200UL /* Clear hash table */
142 #define XEM_ECR_ADD_HASH_ADDR_MASK 0x00000100UL /* Add hash table address */
145 * Interframe Gap Register (IFGR)
147 #define XEM_IFGP_PART1_MASK 0xF8000000UL /* Interframe Gap Part1 */
148 #define XEM_IFGP_PART1_SHIFT 27
149 #define XEM_IFGP_PART2_MASK 0x07C00000UL /* Interframe Gap Part2 */
150 #define XEM_IFGP_PART2_SHIFT 22
153 * Station Address High Register (SAH)
155 #define XEM_SAH_ADDR_MASK 0x0000FFFFUL /* Station address high bytes */
158 * Station Address Low Register (SAL)
160 #define XEM_SAL_ADDR_MASK 0xFFFFFFFFUL /* Station address low bytes */
163 * MII Management Control Register (MGTCR)
165 #define XEM_MGTCR_START_MASK 0x80000000UL /* Start/Busy */
166 #define XEM_MGTCR_RW_NOT_MASK 0x40000000UL /* Read/Write Not (direction) */
167 #define XEM_MGTCR_PHY_ADDR_MASK 0x3E000000UL /* PHY address */
168 #define XEM_MGTCR_PHY_ADDR_SHIFT 25 /* PHY address shift */
169 #define XEM_MGTCR_REG_ADDR_MASK 0x01F00000UL /* Register address */
170 #define XEM_MGTCR_REG_ADDR_SHIFT 20 /* Register addr shift */
171 #define XEM_MGTCR_MII_ENABLE_MASK 0x00080000UL /* Enable MII from EMAC */
172 #define XEM_MGTCR_RD_ERROR_MASK 0x00040000UL /* MII mgmt read error */
175 * MII Management Data Register (MGTDR)
177 #define XEM_MGTDR_DATA_MASK 0x0000FFFFUL /* MII data */
180 * Receive Packet Length Register (RPLR)
182 #define XEM_RPLR_LENGTH_MASK 0x0000FFFFUL /* Receive packet length */
185 * Transmit Packet Length Register (TPLR)
187 #define XEM_TPLR_LENGTH_MASK 0x0000FFFFUL /* Transmit packet length */
190 * Transmit Status Register (TSR)
192 #define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL /* Transmit excess deferral */
193 #define XEM_TSR_FIFO_UNDERRUN_MASK 0x40000000UL /* Packet FIFO underrun */
194 #define XEM_TSR_ATTEMPTS_MASK 0x3E000000UL /* Transmission attempts */
195 #define XEM_TSR_LATE_COLLISION_MASK 0x01000000UL /* Transmit late collision */
198 * Receive Missed Frame Count (RMFC)
200 #define XEM_RMFC_DATA_MASK 0x0000FFFFUL
203 * Receive Collision Count (RCC)
205 #define XEM_RCC_DATA_MASK 0x0000FFFFUL
208 * Receive FCS Error Count (RFCSEC)
210 #define XEM_RFCSEC_DATA_MASK 0x0000FFFFUL
213 * Receive Alignment Error Count (RALN)
215 #define XEM_RAEC_DATA_MASK 0x0000FFFFUL
218 * Transmit Excess Deferral Count (TEDC)
220 #define XEM_TEDC_DATA_MASK 0x0000FFFFUL
223 * EMAC Interrupt Registers (Status and Enable) masks. These registers are
224 * part of the IPIF IP Interrupt registers
226 #define XEM_EIR_XMIT_DONE_MASK 0x00000001UL /* Xmit complete */
227 #define XEM_EIR_RECV_DONE_MASK 0x00000002UL /* Recv complete */
228 #define XEM_EIR_XMIT_ERROR_MASK 0x00000004UL /* Xmit error */
229 #define XEM_EIR_RECV_ERROR_MASK 0x00000008UL /* Recv error */
230 #define XEM_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010UL /* Xmit status fifo empty */
231 #define XEM_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020UL /* Recv length fifo empty */
232 #define XEM_EIR_XMIT_LFIFO_FULL_MASK 0x00000040UL /* Xmit length fifo full */
233 #define XEM_EIR_RECV_LFIFO_OVER_MASK 0x00000080UL /* Recv length fifo
235 #define XEM_EIR_RECV_LFIFO_UNDER_MASK 0x00000100UL /* Recv length fifo
237 #define XEM_EIR_XMIT_SFIFO_OVER_MASK 0x00000200UL /* Xmit status fifo
239 #define XEM_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400UL /* Transmit status fifo
241 #define XEM_EIR_XMIT_LFIFO_OVER_MASK 0x00000800UL /* Transmit length fifo
243 #define XEM_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000UL /* Transmit length fifo
245 #define XEM_EIR_XMIT_PAUSE_MASK 0x00002000UL /* Transmit pause pkt
247 #define XEM_EIR_RECV_DFIFO_OVER_MASK 0x00004000UL /* Receive data fifo
249 #define XEM_EIR_RECV_MISSED_FRAME_MASK 0x00008000UL /* Receive missed frame
251 #define XEM_EIR_RECV_COLLISION_MASK 0x00010000UL /* Receive collision
253 #define XEM_EIR_RECV_FCS_ERROR_MASK 0x00020000UL /* Receive FCS error */
254 #define XEM_EIR_RECV_LEN_ERROR_MASK 0x00040000UL /* Receive length field
256 #define XEM_EIR_RECV_SHORT_ERROR_MASK 0x00080000UL /* Receive short frame
258 #define XEM_EIR_RECV_LONG_ERROR_MASK 0x00100000UL /* Receive long frame
260 #define XEM_EIR_RECV_ALIGN_ERROR_MASK 0x00200000UL /* Receive alignment
263 /**************************** Type Definitions *******************************/
265 /***************** Macros (Inline Functions) Definitions *********************/
267 /*****************************************************************************
269 * Low-level driver macros and functions. The list below provides signatures
270 * to help the user use the macros.
272 * u32 XEmac_mReadReg(u32 BaseAddress, int RegOffset)
273 * void XEmac_mWriteReg(u32 BaseAddress, int RegOffset, u32 Mask)
275 * void XEmac_mSetControlReg(u32 BaseAddress, u32 Mask)
276 * void XEmac_mSetMacAddress(u32 BaseAddress, u8 *AddressPtr)
278 * void XEmac_mEnable(u32 BaseAddress)
279 * void XEmac_mDisable(u32 BaseAddress)
281 * u32 XEmac_mIsTxDone(u32 BaseAddress)
282 * u32 XEmac_mIsRxEmpty(u32 BaseAddress)
284 * void XEmac_SendFrame(u32 BaseAddress, u8 *FramePtr, int Size)
285 * int XEmac_RecvFrame(u32 BaseAddress, u8 *FramePtr)
287 *****************************************************************************/
289 /****************************************************************************/
292 * Read the given register.
294 * @param BaseAddress is the base address of the device
295 * @param RegOffset is the register offset to be read
297 * @return The 32-bit value of the register
301 *****************************************************************************/
302 #define XEmac_mReadReg(BaseAddress, RegOffset) \
303 XIo_In32((BaseAddress) + (RegOffset))
305 /****************************************************************************/
308 * Write the given register.
310 * @param BaseAddress is the base address of the device
311 * @param RegOffset is the register offset to be written
312 * @param Data is the 32-bit value to write to the register
318 *****************************************************************************/
319 #define XEmac_mWriteReg(BaseAddress, RegOffset, Data) \
320 XIo_Out32((BaseAddress) + (RegOffset), (Data))
322 /****************************************************************************/
325 * Set the contents of the control register. Use the XEM_ECR_* constants
326 * defined above to create the bit-mask to be written to the register.
328 * @param BaseAddress is the base address of the device
329 * @param Mask is the 16-bit value to write to the control register
335 *****************************************************************************/
336 #define XEmac_mSetControlReg(BaseAddress, Mask) \
337 XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, (Mask))
339 /****************************************************************************/
342 * Set the station address of the EMAC device.
344 * @param BaseAddress is the base address of the device
345 * @param AddressPtr is a pointer to a 6-byte MAC address
351 *****************************************************************************/
352 #define XEmac_mSetMacAddress(BaseAddress, AddressPtr) \
356 MacAddr = ((AddressPtr)[0] << 8) | (AddressPtr)[1]; \
357 XIo_Out32((BaseAddress) + XEM_SAH_OFFSET, MacAddr); \
359 MacAddr = ((AddressPtr)[2] << 24) | ((AddressPtr)[3] << 16) | \
360 ((AddressPtr)[4] << 8) | (AddressPtr)[5]; \
362 XIo_Out32((BaseAddress) + XEM_SAL_OFFSET, MacAddr); \
365 /****************************************************************************/
368 * Enable the transmitter and receiver. Preserve the contents of the control
371 * @param BaseAddress is the base address of the device
377 *****************************************************************************/
378 #define XEmac_mEnable(BaseAddress) \
381 Control = XIo_In32((BaseAddress) + XEM_ECR_OFFSET); \
382 Control &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK); \
383 Control |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); \
384 XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, Control); \
387 /****************************************************************************/
390 * Disable the transmitter and receiver. Preserve the contents of the control
393 * @param BaseAddress is the base address of the device
399 *****************************************************************************/
400 #define XEmac_mDisable(BaseAddress) \
401 XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, \
402 XIo_In32((BaseAddress) + XEM_ECR_OFFSET) & \
403 ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK))
405 /****************************************************************************/
408 * Check to see if the transmission is complete.
410 * @param BaseAddress is the base address of the device
412 * @return TRUE if it is done, or FALSE if it is not.
416 *****************************************************************************/
417 #define XEmac_mIsTxDone(BaseAddress) \
418 (XIo_In32((BaseAddress) + XEM_ISR_OFFSET) & XEM_EIR_XMIT_DONE_MASK)
420 /****************************************************************************/
423 * Check to see if the receive FIFO is empty.
425 * @param BaseAddress is the base address of the device
427 * @return TRUE if it is empty, or FALSE if it is not.
431 *****************************************************************************/
432 #define XEmac_mIsRxEmpty(BaseAddress) \
433 (!(XIo_In32((BaseAddress) + XEM_ISR_OFFSET) & XEM_EIR_RECV_DONE_MASK))
435 /****************************************************************************/
438 * Reset MII compliant PHY
440 * @param BaseAddress is the base address of the device
446 *****************************************************************************/
447 #define XEmac_mPhyReset(BaseAddress) \
450 Control = XIo_In32((BaseAddress) + XEM_ECR_OFFSET); \
451 Control &= ~XEM_ECR_PHY_ENABLE_MASK; \
452 XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, Control); \
453 Control |= XEM_ECR_PHY_ENABLE_MASK; \
454 XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, Control); \
457 /************************** Function Prototypes ******************************/
459 void XEmac_SendFrame(u32 BaseAddress, u8 * FramePtr, int Size);
460 int XEmac_RecvFrame(u32 BaseAddress, u8 * FramePtr);
462 #endif /* end of protection macro */