1 /******************************************************************************
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
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25 * Xilinx hardware products are not intended for use in life support
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30 * (c) Copyright 2002-2004 Xilinx Inc.
31 * All rights reserved.
34 * You should have received a copy of the GNU General Public License along
35 * with this program; if not, write to the Free Software Foundation, Inc.,
36 * 675 Mass Ave, Cambridge, MA 02139, USA.
38 ******************************************************************************/
39 /*****************************************************************************/
44 * The Xilinx Ethernet driver component. This component supports the Xilinx
45 * Ethernet 10/100 MAC (EMAC).
47 * The Xilinx Ethernet 10/100 MAC supports the following features:
48 * - Simple and scatter-gather DMA operations, as well as simple memory
49 * mapped direct I/O interface (FIFOs).
50 * - Media Independent Interface (MII) for connection to external
51 * 10/100 Mbps PHY transceivers.
52 * - MII management control reads and writes with MII PHYs
53 * - Independent internal transmit and receive FIFOs
54 * - CSMA/CD compliant operations for half-duplex modes
55 * - Programmable PHY reset signal
56 * - Unicast, broadcast, and promiscuous address filtering (no multicast yet)
58 * - Automatic source address insertion or overwrite (programmable)
59 * - Automatic FCS insertion and stripping (programmable)
60 * - Automatic pad insertion and stripping (programmable)
61 * - Pause frame (flow control) detection in full-duplex mode
62 * - Programmable interframe gap
63 * - VLAN frame support.
64 * - Pause frame support
66 * The device driver supports all the features listed above.
68 * <b>Driver Description</b>
70 * The device driver enables higher layer software (e.g., an application) to
71 * communicate to the EMAC. The driver handles transmission and reception of
72 * Ethernet frames, as well as configuration of the controller. It does not
73 * handle protocol stack functionality such as Link Layer Control (LLC) or the
74 * Address Resolution Protocol (ARP). The protocol stack that makes use of the
75 * driver handles this functionality. This implies that the driver is simply a
76 * pass-through mechanism between a protocol stack and the EMAC. A single device
77 * driver can support multiple EMACs.
79 * The driver is designed for a zero-copy buffer scheme. That is, the driver will
80 * not copy buffers. This avoids potential throughput bottlenecks within the
83 * Since the driver is a simple pass-through mechanism between a protocol stack
84 * and the EMAC, no assembly or disassembly of Ethernet frames is done at the
85 * driver-level. This assumes that the protocol stack passes a correctly
86 * formatted Ethernet frame to the driver for transmission, and that the driver
87 * does not validate the contents of an incoming frame
89 * <b>PHY Communication</b>
91 * The driver provides rudimentary read and write functions to allow the higher
92 * layer software to access the PHY. The EMAC provides MII registers for the
93 * driver to access. This management interface can be parameterized away in the
94 * FPGA implementation process. If this is the case, the PHY read and write
95 * functions of the driver return XST_NO_FEATURE.
97 * External loopback is usually supported at the PHY. It is up to the user to
98 * turn external loopback on or off at the PHY. The driver simply provides pass-
99 * through functions for configuring the PHY. The driver does not read, write,
100 * or reset the PHY on its own. All control of the PHY must be done by the user.
102 * <b>Asynchronous Callbacks</b>
104 * The driver services interrupts and passes Ethernet frames to the higher layer
105 * software through asynchronous callback functions. When using the driver
106 * directly (i.e., not with the RTOS protocol stack), the higher layer
107 * software must register its callback functions during initialization. The
108 * driver requires callback functions for received frames, for confirmation of
109 * transmitted frames, and for asynchronous errors.
113 * The driver has no dependencies on the interrupt controller. The driver
114 * provides two interrupt handlers. XEmac_IntrHandlerDma() handles interrupts
115 * when the EMAC is configured with scatter-gather DMA. XEmac_IntrHandlerFifo()
116 * handles interrupts when the EMAC is configured for direct FIFO I/O or simple
117 * DMA. Either of these routines can be connected to the system interrupt
118 * controller by the user.
120 * <b>Interrupt Frequency</b>
122 * When the EMAC is configured with scatter-gather DMA, the frequency of
123 * interrupts can be controlled with the interrupt coalescing features of the
124 * scatter-gather DMA engine. The frequency of interrupts can be adjusted using
125 * the driver API functions for setting the packet count threshold and the packet
128 * The scatter-gather DMA engine only interrupts when the packet count threshold
129 * is reached, instead of interrupting for each packet. A packet is a generic
130 * term used by the scatter-gather DMA engine, and is equivalent to an Ethernet
133 * The packet wait bound is a timer value used during interrupt coalescing to
134 * trigger an interrupt when not enough packets have been received to reach the
135 * packet count threshold.
137 * These values can be tuned by the user to meet their needs. If there appear to
138 * be interrupt latency problems or delays in packet arrival that are longer than
139 * might be expected, the user should verify that the packet count threshold is
140 * set low enough to receive interrupts before the wait bound timer goes off.
142 * <b>Device Reset</b>
144 * Some errors that can occur in the device require a device reset. These errors
145 * are listed in the XEmac_SetErrorHandler() function header. The user's error
146 * handler is responsible for resetting the device and re-configuring it based on
147 * its needs (the driver does not save the current configuration). When
148 * integrating into an RTOS, these reset and re-configure obligations are
149 * taken care of by the Xilinx adapter software if it exists for that RTOS.
151 * <b>Device Configuration</b>
153 * The device can be configured in various ways during the FPGA implementation
154 * process. Configuration parameters are stored in the xemac_g.c files.
155 * A table is defined where each entry contains configuration information
156 * for an EMAC device. This information includes such things as the base address
157 * of the memory-mapped device, the base addresses of IPIF, DMA, and FIFO modules
158 * within the device, and whether the device has DMA, counter registers,
159 * multicast support, MII support, and flow control.
161 * The driver tries to use the features built into the device. So if, for
162 * example, the hardware is configured with scatter-gather DMA, the driver
163 * expects to start the scatter-gather channels and expects that the user has set
164 * up the buffer descriptor lists already. If the user expects to use the driver
165 * in a mode different than how the hardware is configured, the user should
166 * modify the configuration table to reflect the mode to be used. Modifying the
167 * configuration table is a workaround for now until we get some experience with
168 * how users are intending to use the hardware in its different configurations.
169 * For example, if the hardware is built with scatter-gather DMA but the user is
170 * intending to use only simple DMA, the user either needs to modify the config
171 * table as a workaround or rebuild the hardware with only simple DMA. The
172 * recommendation at this point is to build the hardware with the features you
173 * intend to use. If you're inclined to modify the table, do so before the call
174 * to XEmac_Initialize(). Here is a snippet of code that changes a device to
175 * simple DMA (the hardware needs to have DMA for this to work of course):
177 * XEmac_Config *ConfigPtr;
179 * ConfigPtr = XEmac_LookupConfig(DeviceId);
180 * ConfigPtr->IpIfDmaConfig = XEM_CFG_SIMPLE_DMA;
185 * Simple DMA is supported through the FIFO functions, FifoSend and FifoRecv, of
186 * the driver (i.e., there is no separate interface for it). The driver makes use
187 * of the DMA engine for a simple DMA transfer if the device is configured with
188 * DMA, otherwise it uses the FIFOs directly. While the simple DMA interface is
189 * therefore transparent to the user, the caching of network buffers is not.
190 * If the device is configured with DMA and the FIFO interface is used, the user
191 * must ensure that the network buffers are not cached or are cache coherent,
192 * since DMA will be used to transfer to and from the Emac device. If the device
193 * is configured with DMA and the user really wants to use the FIFOs directly,
194 * the user should rebuild the hardware without DMA. If unable to do this, there
195 * is a workaround (described above in Device Configuration) to modify the
196 * configuration table of the driver to fake the driver into thinking the device
197 * has no DMA. A code snippet follows:
199 * XEmac_Config *ConfigPtr;
201 * ConfigPtr = XEmac_LookupConfig(DeviceId);
202 * ConfigPtr->IpIfDmaConfig = XEM_CFG_NO_DMA;
207 * Asserts are used within all Xilinx drivers to enforce constraints on argument
208 * values. Asserts can be turned off on a system-wide basis by defining, at
209 * compile time, the NDEBUG identifier. By default, asserts are turned on and it
210 * is recommended that users leave asserts on during development.
212 * <b>Building the driver</b>
214 * The XEmac driver is composed of several source files. Why so many? This
215 * allows the user to build and link only those parts of the driver that are
216 * necessary. Since the EMAC hardware can be configured in various ways (e.g.,
217 * with or without DMA), the driver too can be built with varying features.
218 * For the most part, this means that besides always linking in xemac.c, you
219 * link in only the driver functionality you want. Some of the choices you have
220 * are polled vs. interrupt, interrupt with FIFOs only vs. interrupt with DMA,
221 * self-test diagnostics, and driver statistics. Note that currently the DMA code
222 * must be linked in, even if you don't have DMA in the device.
226 * Xilinx drivers are typically composed of two components, one is the driver
227 * and the other is the adapter. The driver is independent of OS and processor
228 * and is intended to be highly portable. The adapter is OS-specific and
229 * facilitates communication between the driver and an OS.
231 * This driver is intended to be RTOS and processor independent. It works
232 * with physical addresses only. Any needs for dynamic memory management,
233 * threads or thread mutual exclusion, virtual memory, or cache control must
234 * be satisfied by the layer above this driver.
237 * MODIFICATION HISTORY:
239 * Ver Who Date Changes
240 * ----- ---- -------- -------------------------------------------------------
241 * 1.00a rpm 07/31/01 First release
242 * 1.00b rpm 02/20/02 Repartitioned files and functions
243 * 1.00b rpm 10/08/02 Replaced HasSgDma boolean with IpifDmaConfig enumerated
244 * configuration parameter
245 * 1.00c rpm 12/05/02 New version includes support for simple DMA and the delay
247 * 1.00c rpm 02/03/03 The XST_DMA_SG_COUNT_EXCEEDED return code was removed
248 * from SetPktThreshold in the internal DMA driver. Also
249 * avoided compiler warnings by initializing Result in the
250 * DMA interrupt service routines.
253 ******************************************************************************/
255 #ifndef XEMAC_H /* prevent circular inclusions */
256 #define XEMAC_H /* by using protection macros */
258 /***************************** Include Files *********************************/
260 #include "xbasic_types.h"
262 #include "xparameters.h"
263 #include "xpacket_fifo_v1_00_b.h" /* Uses v1.00b of Packet Fifo */
264 #include "xdma_channel.h"
266 /************************** Constant Definitions *****************************/
271 #define XEM_DEVICE_NAME "xemac"
272 #define XEM_DEVICE_DESC "Xilinx Ethernet 10/100 MAC"
274 /** @name Configuration options
276 * Device configuration options (see the XEmac_SetOptions() and
277 * XEmac_GetOptions() for information on how to use these options)
282 * XEM_BROADCAST_OPTION Broadcast addressing on or off (default is on)
283 * XEM_UNICAST_OPTION Unicast addressing on or off (default is on)
284 * XEM_PROMISC_OPTION Promiscuous addressing on or off (default is off)
285 * XEM_FDUPLEX_OPTION Full duplex on or off (default is off)
286 * XEM_POLLED_OPTION Polled mode on or off (default is off)
287 * XEM_LOOPBACK_OPTION Internal loopback on or off (default is off)
288 * XEM_FLOW_CONTROL_OPTION Interpret pause frames in full duplex mode
290 * XEM_INSERT_PAD_OPTION Pad short frames on transmit (default is on)
291 * XEM_INSERT_FCS_OPTION Insert FCS (CRC) on transmit (default is on)
292 * XEM_INSERT_ADDR_OPTION Insert source address on transmit (default is on)
293 * XEM_OVWRT_ADDR_OPTION Overwrite source address on transmit. This is
294 * only used if source address insertion is on.
296 * XEM_STRIP_PAD_FCS_OPTION Strip FCS and padding from received frames
300 #define XEM_UNICAST_OPTION 0x00000001UL
301 #define XEM_BROADCAST_OPTION 0x00000002UL
302 #define XEM_PROMISC_OPTION 0x00000004UL
303 #define XEM_FDUPLEX_OPTION 0x00000008UL
304 #define XEM_POLLED_OPTION 0x00000010UL
305 #define XEM_LOOPBACK_OPTION 0x00000020UL
306 #define XEM_FLOW_CONTROL_OPTION 0x00000080UL
307 #define XEM_INSERT_PAD_OPTION 0x00000100UL
308 #define XEM_INSERT_FCS_OPTION 0x00000200UL
309 #define XEM_INSERT_ADDR_OPTION 0x00000400UL
310 #define XEM_OVWRT_ADDR_OPTION 0x00000800UL
311 #define XEM_STRIP_PAD_FCS_OPTION 0x00002000UL
315 * XEM_MULTICAST_OPTION Multicast addressing on or off (default is off)
317 /* NOT SUPPORTED YET... */
318 #define XEM_MULTICAST_OPTION 0x00000040UL
321 * Some default values for interrupt coalescing within the scatter-gather
324 #define XEM_SGDMA_DFT_THRESHOLD 1 /* Default pkt threshold */
325 #define XEM_SGDMA_MAX_THRESHOLD 255 /* Maximum pkt theshold */
326 #define XEM_SGDMA_DFT_WAITBOUND 5 /* Default pkt wait bound (msec) */
327 #define XEM_SGDMA_MAX_WAITBOUND 1023 /* Maximum pkt wait bound (msec) */
330 * Direction identifiers. These are used for setting values like packet
331 * thresholds and wait bound for specific channels
337 * Arguments to SgSend function to indicate whether to hold off starting
338 * the scatter-gather engine.
340 #define XEM_SGDMA_NODELAY 0 /* start SG DMA immediately */
341 #define XEM_SGDMA_DELAY 1 /* do not start SG DMA */
344 * Constants to determine the configuration of the hardware device. They are
345 * used to allow the driver to verify it can operate with the hardware.
347 #define XEM_CFG_NO_IPIF 0 /* Not supported by the driver */
348 #define XEM_CFG_NO_DMA 1 /* No DMA */
349 #define XEM_CFG_SIMPLE_DMA 2 /* Simple DMA */
350 #define XEM_CFG_DMA_SG 3 /* DMA scatter gather */
353 * The next few constants help upper layers determine the size of memory
354 * pools used for Ethernet buffers and descriptor lists.
356 #define XEM_MAC_ADDR_SIZE 6 /* six-byte MAC address */
357 #define XEM_MTU 1500 /* max size of Ethernet frame */
358 #define XEM_HDR_SIZE 14 /* size of Ethernet header */
359 #define XEM_HDR_VLAN_SIZE 18 /* size of Ethernet header with VLAN */
360 #define XEM_TRL_SIZE 4 /* size of Ethernet trailer (FCS) */
361 #define XEM_MAX_FRAME_SIZE (XEM_MTU + XEM_HDR_SIZE + XEM_TRL_SIZE)
362 #define XEM_MAX_VLAN_FRAME_SIZE (XEM_MTU + XEM_HDR_VLAN_SIZE + XEM_TRL_SIZE)
365 * Define a default number of send and receive buffers
367 #define XEM_MIN_RECV_BUFS 32 /* minimum # of recv buffers */
368 #define XEM_DFT_RECV_BUFS 64 /* default # of recv buffers */
370 #define XEM_MIN_SEND_BUFS 16 /* minimum # of send buffers */
371 #define XEM_DFT_SEND_BUFS 32 /* default # of send buffers */
373 #define XEM_MIN_BUFFERS (XEM_MIN_RECV_BUFS + XEM_MIN_SEND_BUFS)
374 #define XEM_DFT_BUFFERS (XEM_DFT_RECV_BUFS + XEM_DFT_SEND_BUFS)
377 * Define the number of send and receive buffer descriptors, used for
380 #define XEM_MIN_RECV_DESC 16 /* minimum # of recv descriptors */
381 #define XEM_DFT_RECV_DESC 32 /* default # of recv descriptors */
383 #define XEM_MIN_SEND_DESC 8 /* minimum # of send descriptors */
384 #define XEM_DFT_SEND_DESC 16 /* default # of send descriptors */
386 /**************************** Type Definitions *******************************/
389 * Ethernet statistics (see XEmac_GetStats() and XEmac_ClearStats())
392 u32 XmitFrames; /**< Number of frames transmitted */
393 u32 XmitBytes; /**< Number of bytes transmitted */
394 u32 XmitLateCollisionErrors;
395 /**< Number of transmission failures
396 due to late collisions */
397 u32 XmitExcessDeferral; /**< Number of transmission failures
398 due o excess collision deferrals */
399 u32 XmitOverrunErrors; /**< Number of transmit overrun errors */
400 u32 XmitUnderrunErrors; /**< Number of transmit underrun errors */
401 u32 RecvFrames; /**< Number of frames received */
402 u32 RecvBytes; /**< Number of bytes received */
403 u32 RecvFcsErrors; /**< Number of frames discarded due
405 u32 RecvAlignmentErrors; /**< Number of frames received with
407 u32 RecvOverrunErrors; /**< Number of frames discarded due
409 u32 RecvUnderrunErrors; /**< Number of recv underrun errors */
410 u32 RecvMissedFrameErrors;
411 /**< Number of frames missed by MAC */
412 u32 RecvCollisionErrors; /**< Number of frames discarded due
414 u32 RecvLengthFieldErrors;
415 /**< Number of frames discarded with
416 invalid length field */
417 u32 RecvShortErrors; /**< Number of short frames discarded */
418 u32 RecvLongErrors; /**< Number of long frames discarded */
419 u32 DmaErrors; /**< Number of DMA errors since init */
420 u32 FifoErrors; /**< Number of FIFO errors since init */
421 u32 RecvInterrupts; /**< Number of receive interrupts */
422 u32 XmitInterrupts; /**< Number of transmit interrupts */
423 u32 EmacInterrupts; /**< Number of MAC (device) interrupts */
424 u32 TotalIntrs; /**< Total interrupts */
428 * This typedef contains configuration information for a device.
431 u16 DeviceId; /**< Unique ID of device */
432 u32 BaseAddress; /**< Register base address */
433 u32 HasCounters; /**< Does device have counters? */
434 u8 IpIfDmaConfig; /**< IPIF/DMA hardware configuration */
435 u32 HasMii; /**< Does device support MII? */
439 /** @name Typedefs for callbacks
440 * Callback functions.
444 * Callback when data is sent or received with scatter-gather DMA.
446 * @param CallBackRef is a callback reference passed in by the upper layer
447 * when setting the callback functions, and passed back to the upper
448 * layer when the callback is invoked.
449 * @param BdPtr is a pointer to the first buffer descriptor in a list of
450 * buffer descriptors.
451 * @param NumBds is the number of buffer descriptors in the list pointed
454 typedef void (*XEmac_SgHandler) (void *CallBackRef, XBufDescriptor * BdPtr,
458 * Callback when data is sent or received with direct FIFO communication or
459 * simple DMA. The user typically defines two callacks, one for send and one
462 * @param CallBackRef is a callback reference passed in by the upper layer
463 * when setting the callback functions, and passed back to the upper
464 * layer when the callback is invoked.
466 typedef void (*XEmac_FifoHandler) (void *CallBackRef);
469 * Callback when an asynchronous error occurs.
471 * @param CallBackRef is a callback reference passed in by the upper layer
472 * when setting the callback functions, and passed back to the upper
473 * layer when the callback is invoked.
474 * @param ErrorCode is a Xilinx error code defined in xstatus.h. Also see
475 * XEmac_SetErrorHandler() for a description of possible errors.
477 typedef void (*XEmac_ErrorHandler) (void *CallBackRef, XStatus ErrorCode);
481 * The XEmac driver instance data. The user is required to allocate a
482 * variable of this type for every EMAC device in the system. A pointer
483 * to a variable of this type is then passed to the driver API functions.
486 u32 BaseAddress; /* Base address (of IPIF) */
487 u32 IsStarted; /* Device is currently started */
488 u32 IsReady; /* Device is initialized and ready */
489 u32 IsPolled; /* Device is in polled mode */
490 u8 IpIfDmaConfig; /* IPIF/DMA hardware configuration */
491 u32 HasMii; /* Does device support MII? */
492 u32 HasMulticastHash; /* Does device support multicast hash table? */
495 XPacketFifoV100b RecvFifo; /* FIFO used to receive frames */
496 XPacketFifoV100b SendFifo; /* FIFO used to send frames */
501 XEmac_FifoHandler FifoRecvHandler; /* for non-DMA/simple DMA interrupts */
503 XEmac_FifoHandler FifoSendHandler; /* for non-DMA/simple DMA interrupts */
505 XEmac_ErrorHandler ErrorHandler; /* for asynchronous errors */
508 XDmaChannel RecvChannel; /* DMA receive channel driver */
509 XDmaChannel SendChannel; /* DMA send channel driver */
511 XEmac_SgHandler SgRecvHandler; /* callback for scatter-gather DMA */
513 XEmac_SgHandler SgSendHandler; /* callback for scatter-gather DMA */
517 /***************** Macros (Inline Functions) Definitions *********************/
519 /*****************************************************************************/
522 * This macro determines if the device is currently configured for
523 * scatter-gather DMA.
525 * @param InstancePtr is a pointer to the XEmac instance to be worked on.
529 * Boolean TRUE if the device is configured for scatter-gather DMA, or FALSE
534 * Signature: u32 XEmac_mIsSgDma(XEmac *InstancePtr)
536 ******************************************************************************/
537 #define XEmac_mIsSgDma(InstancePtr) \
538 ((InstancePtr)->IpIfDmaConfig == XEM_CFG_DMA_SG)
540 /*****************************************************************************/
543 * This macro determines if the device is currently configured for simple DMA.
545 * @param InstancePtr is a pointer to the XEmac instance to be worked on.
549 * Boolean TRUE if the device is configured for simple DMA, or FALSE otherwise
553 * Signature: u32 XEmac_mIsSimpleDma(XEmac *InstancePtr)
555 ******************************************************************************/
556 #define XEmac_mIsSimpleDma(InstancePtr) \
557 ((InstancePtr)->IpIfDmaConfig == XEM_CFG_SIMPLE_DMA)
559 /*****************************************************************************/
562 * This macro determines if the device is currently configured with DMA (either
563 * simple DMA or scatter-gather DMA)
565 * @param InstancePtr is a pointer to the XEmac instance to be worked on.
569 * Boolean TRUE if the device is configured with DMA, or FALSE otherwise
573 * Signature: u32 XEmac_mIsDma(XEmac *InstancePtr)
575 ******************************************************************************/
576 #define XEmac_mIsDma(InstancePtr) \
577 (XEmac_mIsSimpleDma(InstancePtr) || XEmac_mIsSgDma(InstancePtr))
579 /************************** Function Prototypes ******************************/
582 * Initialization functions in xemac.c
584 XStatus XEmac_Initialize(XEmac * InstancePtr, u16 DeviceId);
585 XStatus XEmac_Start(XEmac * InstancePtr);
586 XStatus XEmac_Stop(XEmac * InstancePtr);
587 void XEmac_Reset(XEmac * InstancePtr);
588 XEmac_Config *XEmac_LookupConfig(u16 DeviceId);
591 * Diagnostic functions in xemac_selftest.c
593 XStatus XEmac_SelfTest(XEmac * InstancePtr);
596 * Polled functions in xemac_polled.c
598 XStatus XEmac_PollSend(XEmac * InstancePtr, u8 * BufPtr, u32 ByteCount);
599 XStatus XEmac_PollRecv(XEmac * InstancePtr, u8 * BufPtr, u32 * ByteCountPtr);
602 * Interrupts with scatter-gather DMA functions in xemac_intr_dma.c
604 XStatus XEmac_SgSend(XEmac * InstancePtr, XBufDescriptor * BdPtr, int Delay);
605 XStatus XEmac_SgRecv(XEmac * InstancePtr, XBufDescriptor * BdPtr);
606 XStatus XEmac_SetPktThreshold(XEmac * InstancePtr, u32 Direction, u8 Threshold);
607 XStatus XEmac_GetPktThreshold(XEmac * InstancePtr, u32 Direction,
609 XStatus XEmac_SetPktWaitBound(XEmac * InstancePtr, u32 Direction,
611 XStatus XEmac_GetPktWaitBound(XEmac * InstancePtr, u32 Direction,
613 XStatus XEmac_SetSgRecvSpace(XEmac * InstancePtr, u32 * MemoryPtr,
615 XStatus XEmac_SetSgSendSpace(XEmac * InstancePtr, u32 * MemoryPtr,
617 void XEmac_SetSgRecvHandler(XEmac * InstancePtr, void *CallBackRef,
618 XEmac_SgHandler FuncPtr);
619 void XEmac_SetSgSendHandler(XEmac * InstancePtr, void *CallBackRef,
620 XEmac_SgHandler FuncPtr);
622 void XEmac_IntrHandlerDma(void *InstancePtr); /* interrupt handler */
625 * Interrupts with direct FIFO functions in xemac_intr_fifo.c. Also used
628 XStatus XEmac_FifoSend(XEmac * InstancePtr, u8 * BufPtr, u32 ByteCount);
629 XStatus XEmac_FifoRecv(XEmac * InstancePtr, u8 * BufPtr, u32 * ByteCountPtr);
630 void XEmac_SetFifoRecvHandler(XEmac * InstancePtr, void *CallBackRef,
631 XEmac_FifoHandler FuncPtr);
632 void XEmac_SetFifoSendHandler(XEmac * InstancePtr, void *CallBackRef,
633 XEmac_FifoHandler FuncPtr);
635 void XEmac_IntrHandlerFifo(void *InstancePtr); /* interrupt handler */
638 * General interrupt-related functions in xemac_intr.c
640 void XEmac_SetErrorHandler(XEmac * InstancePtr, void *CallBackRef,
641 XEmac_ErrorHandler FuncPtr);
644 * MAC configuration in xemac_options.c
646 XStatus XEmac_SetOptions(XEmac * InstancePtr, u32 OptionFlag);
647 u32 XEmac_GetOptions(XEmac * InstancePtr);
648 XStatus XEmac_SetMacAddress(XEmac * InstancePtr, u8 * AddressPtr);
649 void XEmac_GetMacAddress(XEmac * InstancePtr, u8 * BufferPtr);
650 XStatus XEmac_SetInterframeGap(XEmac * InstancePtr, u8 Part1, u8 Part2);
651 void XEmac_GetInterframeGap(XEmac * InstancePtr, u8 * Part1Ptr, u8 * Part2Ptr);
654 * Multicast functions in xemac_multicast.c (not supported by EMAC yet)
656 XStatus XEmac_MulticastAdd(XEmac * InstancePtr, u8 * AddressPtr);
657 XStatus XEmac_MulticastClear(XEmac * InstancePtr);
660 * PHY configuration in xemac_phy.c
662 XStatus XEmac_PhyRead(XEmac * InstancePtr, u32 PhyAddress,
663 u32 RegisterNum, u16 * PhyDataPtr);
664 XStatus XEmac_PhyWrite(XEmac * InstancePtr, u32 PhyAddress,
665 u32 RegisterNum, u16 PhyData);
668 * Statistics in xemac_stats.c
670 void XEmac_GetStats(XEmac * InstancePtr, XEmac_Stats * StatsPtr);
671 void XEmac_ClearStats(XEmac * InstancePtr);
673 #endif /* end of protection macro */