board/xilinx/versal/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2018 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <fdtdec.h>
   9 #include <malloc.h>
  10 #include <time.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/hardware.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <dm/device.h>
  15 #include <dm/uclass.h>
  16 #include <versalpl.h>
  17 #include <linux/sizes.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 #if defined(CONFIG_FPGA_VERSALPL)
  22 static xilinx_desc versalpl = XILINX_VERSAL_DESC;
  23 #endif
  24
  25 int board_init(void)
  26 {
  27         printf("EL Level:\tEL%d\n", current_el());
  28
  29 #if defined(CONFIG_FPGA_VERSALPL)
  30         fpga_init();
  31         fpga_add(fpga_xilinx, &versalpl);
  32 #endif
  33
  34         return 0;
  35 }
  36
  37 int board_early_init_r(void)
  38 {
  39         u32 val;
  40
  41         if (current_el() != 3)
  42                 return 0;
  43
  44         debug("iou_switch ctrl div0 %x\n",
  45               readl(&crlapb_base->iou_switch_ctrl));
  46
  47         writel(IOU_SWITCH_CTRL_CLKACT_BIT |
  48                (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
  49                &crlapb_base->iou_switch_ctrl);
  50
  51         /* Global timer init - Program time stamp reference clk */
  52         val = readl(&crlapb_base->timestamp_ref_ctrl);
  53         val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
  54         writel(val, &crlapb_base->timestamp_ref_ctrl);
  55
  56         debug("ref ctrl 0x%x\n",
  57               readl(&crlapb_base->timestamp_ref_ctrl));
  58
  59         /* Clear reset of timestamp reg */
  60         writel(0, &crlapb_base->rst_timestamp);
  61
  62         /*
  63          * Program freq register in System counter and
  64          * enable system counter.
  65          */
  66         writel(COUNTER_FREQUENCY,
  67                &iou_scntr_secure->base_frequency_id_register);
  68
  69         debug("counter val 0x%x\n",
  70               readl(&iou_scntr_secure->base_frequency_id_register));
  71
  72         writel(IOU_SCNTRS_CONTROL_EN,
  73                &iou_scntr_secure->counter_control_register);
  74
  75         debug("scntrs control 0x%x\n",
  76               readl(&iou_scntr_secure->counter_control_register));
  77         debug("timer 0x%llx\n", get_ticks());
  78         debug("timer 0x%llx\n", get_ticks());
  79
  80         return 0;
  81 }
  82
  83 int board_late_init(void)
  84 {
  85         u32 reg = 0;
  86         u8 bootmode;
  87         struct udevice *dev;
  88         int bootseq = -1;
  89         int bootseq_len = 0;
  90         int env_targets_len = 0;
  91         const char *mode;
  92         char *new_targets;
  93         char *env_targets;
  94         ulong initrd_hi;
  95
  96         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
  97                 debug("Saved variables - Skipping\n");
  98                 return 0;
  99         }
 100
 101         reg = readl(&crp_base->boot_mode_usr);
 102
 103         if (reg >> BOOT_MODE_ALT_SHIFT)
 104                 reg >>= BOOT_MODE_ALT_SHIFT;
 105
 106         bootmode = reg & BOOT_MODES_MASK;
 107
 108         puts("Bootmode: ");
 109         switch (bootmode) {
 110         case USB_MODE:
 111                 puts("USB_MODE\n");
 112                 mode = "dfu_usb";
 113                 break;
 114         case JTAG_MODE:
 115                 puts("JTAG_MODE\n");
 116                 mode = "jtag pxe dhcp";
 117                 break;
 118         case QSPI_MODE_24BIT:
 119                 puts("QSPI_MODE_24\n");
 120                 mode = "xspi0";
 121                 break;
 122         case QSPI_MODE_32BIT:
 123                 puts("QSPI_MODE_32\n");
 124                 mode = "xspi0";
 125                 break;
 126         case OSPI_MODE:
 127                 puts("OSPI_MODE\n");
 128                 mode = "xspi0";
 129                 break;
 130         case EMMC_MODE:
 131                 puts("EMMC_MODE\n");
 132                 mode = "mmc0";
 133                 break;
 134         case SD_MODE:
 135                 puts("SD_MODE\n");
 136                 if (uclass_get_device_by_name(UCLASS_MMC,
 137                                               "sdhci@f1040000", &dev)) {
 138                         puts("Boot from SD0 but without SD0 enabled!\n");
 139                         return -1;
 140                 }
 141                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 142
 143                 mode = "mmc";
 144                 bootseq = dev->seq;
 145                 break;
 146         case SD1_LSHFT_MODE:
 147                 puts("LVL_SHFT_");
 148                 /* fall through */
 149         case SD_MODE1:
 150                 puts("SD_MODE1\n");
 151                 if (uclass_get_device_by_name(UCLASS_MMC,
 152                                               "sdhci@f1050000", &dev)) {
 153                         puts("Boot from SD1 but without SD1 enabled!\n");
 154                         return -1;
 155                 }
 156                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 157
 158                 mode = "mmc";
 159                 bootseq = dev->seq;
 160                 break;
 161         default:
 162                 mode = "";
 163                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 164                 break;
 165         }
 166
 167         if (bootseq >= 0) {
 168                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 169                 debug("Bootseq len: %x\n", bootseq_len);
 170         }
 171
 172         /*
 173          * One terminating char + one byte for space between mode
 174          * and default boot_targets
 175          */
 176         env_targets = env_get("boot_targets");
 177         if (env_targets)
 178                 env_targets_len = strlen(env_targets);
 179
 180         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 181                              bootseq_len);
 182         if (!new_targets)
 183                 return -ENOMEM;
 184
 185         if (bootseq >= 0)
 186                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 187                         env_targets ? env_targets : "");
 188         else
 189                 sprintf(new_targets, "%s %s", mode,
 190                         env_targets ? env_targets : "");
 191
 192         env_set("boot_targets", new_targets);
 193
 194         initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
 195         initrd_hi = round_down(initrd_hi, SZ_16M);
 196         env_set_addr("initrd_high", (void *)initrd_hi);
 197
 198         return 0;
 199 }
 200
 201 int dram_init_banksize(void)
 202 {
 203         int ret;
 204
 205         ret = fdtdec_setup_memory_banksize();
 206         if (ret)
 207                 return ret;
 208
 209         mem_map_fill();
 210
 211         return 0;
 212 }
 213
 214 int dram_init(void)
 215 {
 216         if (fdtdec_setup_mem_size_base() != 0)
 217                 return -EINVAL;
 218
 219         return 0;
 220 }
 221
 222 void reset_cpu(ulong addr)
 223 {
 224 }