1 /*********************************************************************
3 # CAUTION: This file is automatically generated by libgen.
4 # Version: Xilinx EDK 6.3 EDK_Gmm.12.3
5 # Description: U-BOOT Configuration File
6 # Michal Simek - monstr@monstr.eu
8 **********************************************************************/
10 /* System Clock Frequency */
11 #define XILINX_CLOCK_FREQ 66666667
13 /* Interrupt controller is intc_0 */
14 #define XILINX_INTC_BASEADDR 0xd1000fc0
15 #define XILINX_INTC_NUM_INTR_INPUTS 12
17 /* Timer pheriphery is opb_timer_0 */
18 #define XILINX_TIMER_BASEADDR 0xa2000000
19 #define XILINX_TIMER_IRQ 0
21 /* Uart pheriphery is console_uart */
22 #define XILINX_UART_BASEADDR 0xa0000000
23 #define XILINX_UART_BAUDRATE 115200
25 /* GPIO is opb_gpio_0*/
26 #define XILINX_GPIO_BASEADDR 0x90000000
28 /* Flash Memory is opb_emc_0 */
29 #define XILINX_FLASH_START 0x28000000
30 #define XILINX_FLASH_SIZE 0x00800000
32 /* Main Memory is plb_ddr_0 */
33 #define XILINX_RAM_START 0x10000000
34 #define XILINX_RAM_SIZE 0x10000000
36 /* Sysace Controller is opb_sysace_0 */
37 #define XILINX_SYSACE_BASEADDR 0xCF000000
38 #define XILINX_SYSACE_HIGHADDR 0xCF0001FF
39 #define XILINX_SYSACE_MEM_WIDTH 16
41 /* Ethernet controller is opb_ethernet_0 */
42 #define XPAR_XEMAC_NUM_INSTANCES 1
43 #define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
44 #define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000
45 #define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF
46 #define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
47 #define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
48 #define XPAR_OPB_ETHERNET_0_MII_EXIST 1