1 /*******************************************************************
3 * CAUTION: This file is automatically generated by libgen.
4 * Version: Xilinx EDK 6.2 EDK_Gm.11
7 * Copyright (c) 2003 Xilinx, Inc. All rights reserved.
9 * Description: Driver parameters
11 *******************************************************************/
13 /******************************************************************/
15 /* U-Boot Redefines */
17 /******************************************************************/
19 #define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000)
20 #define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR
21 #define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
22 #define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID
23 #define XPAR_UARTNS550_1_BASEADDR (XPAR_OPB_UART16550_1_BASEADDR+0x1000)
24 #define XPAR_UARTNS550_1_HIGHADDR XPAR_OPB_UART16550_1_HIGHADDR
25 #define XPAR_UARTNS550_1_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
26 #define XPAR_UARTNS550_1_DEVICE_ID XPAR_OPB_UART16550_1_DEVICE_ID
28 /******************************************************************/
30 #define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR
31 #define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR
32 #define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR
33 #define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID
35 /******************************************************************/
37 #define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR
38 #define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR
39 #define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT
40 #define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST
41 #define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST
42 #define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID
44 /******************************************************************/
46 #define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ
48 /******************************************************************/
50 #define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400
51 #define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF
52 #define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0
54 /******************************************************************/
56 #define XPAR_XPCI_NUM_INSTANCES 1
57 #define XPAR_XPCI_CLOCK_HZ 33333333
58 #define XPAR_OPB_PCI_REF_0_DEVICE_ID 0
59 #define XPAR_OPB_PCI_REF_0_BASEADDR 0x20000000
60 #define XPAR_OPB_PCI_REF_0_HIGHADDR 0x3FFFFFFF
61 #define XPAR_OPB_PCI_REF_0_CONFIG_ADDR 0x3C000000
62 #define XPAR_OPB_PCI_REF_0_CONFIG_DATA 0x3C000004
63 #define XPAR_OPB_PCI_REF_0_LCONFIG_ADDR 0x3E000000
64 #define XPAR_OPB_PCI_REF_0_MEM_BASEADDR 0x20000000
65 #define XPAR_OPB_PCI_REF_0_MEM_HIGHADDR 0x37FFFFFF
66 #define XPAR_OPB_PCI_REF_0_IO_BASEADDR 0x38000000
67 #define XPAR_OPB_PCI_REF_0_IO_HIGHADDR 0x3BFFFFFF
69 /******************************************************************/
71 #define XPAR_XEMAC_NUM_INSTANCES 1
72 #define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000
73 #define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF
74 #define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
75 #define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
76 #define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
77 #define XPAR_OPB_ETHERNET_0_MII_EXIST 1
79 /******************************************************************/
81 #define XPAR_MY_OPB_GPIO_0_DEVICE_ID_0 0
82 #define XPAR_MY_OPB_GPIO_0_BASEADDR_0 0x90000000
83 #define XPAR_MY_OPB_GPIO_0_HIGHADDR_0 (0x90000000+0x7)
84 #define XPAR_MY_OPB_GPIO_0_DEVICE_ID_1 1
85 #define XPAR_MY_OPB_GPIO_0_BASEADDR_1 (0x90000000+0x8)
86 #define XPAR_MY_OPB_GPIO_0_HIGHADDR_1 (0x90000000+0x1F)
87 #define XPAR_XGPIO_NUM_INSTANCES 2
89 /******************************************************************/
91 #define XPAR_XIIC_NUM_INSTANCES 1
92 #define XPAR_OPB_IIC_0_BASEADDR 0xA8000000
93 #define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF
94 #define XPAR_OPB_IIC_0_DEVICE_ID 0
95 #define XPAR_OPB_IIC_0_TEN_BIT_ADR 0
97 /******************************************************************/
99 #define XPAR_XUARTNS550_NUM_INSTANCES 2
100 #define XPAR_XUARTNS550_CLOCK_HZ 100000000
101 #define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000
102 #define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF
103 #define XPAR_OPB_UART16550_0_DEVICE_ID 0
104 #define XPAR_OPB_UART16550_1_BASEADDR 0xA0010000
105 #define XPAR_OPB_UART16550_1_HIGHADDR 0xA0011FFF
106 #define XPAR_OPB_UART16550_1_DEVICE_ID 1
108 /******************************************************************/
110 #define XPAR_XSPI_NUM_INSTANCES 1
111 #define XPAR_OPB_SPI_0_BASEADDR 0xA4000000
112 #define XPAR_OPB_SPI_0_HIGHADDR 0xA400007F
113 #define XPAR_OPB_SPI_0_DEVICE_ID 0
114 #define XPAR_OPB_SPI_0_FIFO_EXIST 1
115 #define XPAR_OPB_SPI_0_SPI_SLAVE_ONLY 0
116 #define XPAR_OPB_SPI_0_NUM_SS_BITS 1
118 /******************************************************************/
120 #define XPAR_XPS2_NUM_INSTANCES 2
121 #define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0
122 #define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000
123 #define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F)
124 #define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1
125 #define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000)
126 #define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F)
128 /******************************************************************/
130 #define XPAR_XTOUCHSCREEN_NUM_INSTANCES 1
131 #define XPAR_OPB_TSD_REF_0_BASEADDR 0xAA000000
132 #define XPAR_OPB_TSD_REF_0_HIGHADDR 0xAA000007
133 #define XPAR_OPB_TSD_REF_0_DEVICE_ID 0
135 /******************************************************************/
137 #define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000
138 #define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF
139 #define XPAR_OPB_PAR_PORT_REF_0_BASEADDR 0x90010000
140 #define XPAR_OPB_PAR_PORT_REF_0_HIGHADDR 0x900100FF
141 #define XPAR_PLB_DDR_0_BASEADDR 0x00000000
142 #define XPAR_PLB_DDR_0_HIGHADDR 0x0FFFFFFF
144 /******************************************************************/
146 #define XPAR_XINTC_HAS_IPR 1
147 #define XPAR_INTC_MAX_NUM_INTR_INPUTS 18
148 #define XPAR_XINTC_USE_DCR 0
149 #define XPAR_XINTC_NUM_INSTANCES 1
150 #define XPAR_DCR_INTC_0_BASEADDR 0xD0000FC0
151 #define XPAR_DCR_INTC_0_HIGHADDR 0xD0000FDF
152 #define XPAR_DCR_INTC_0_DEVICE_ID 0
153 #define XPAR_DCR_INTC_0_KIND_OF_INTR 0x00038000
155 /******************************************************************/
157 #define XPAR_DCR_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 0
158 #define XPAR_DCR_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 1
159 #define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_TEMP_CRIT_INTR 2
160 #define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_IRQ_INTR 3
161 #define XPAR_DCR_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 4
162 #define XPAR_DCR_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 5
163 #define XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 6
164 #define XPAR_DCR_INTC_0_OPB_UART16550_1_IP2INTC_IRPT_INTR 7
165 #define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8
166 #define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 9
167 #define XPAR_DCR_INTC_0_OPB_SPI_0_IP2INTC_IRPT_INTR 10
168 #define XPAR_DCR_INTC_0_OPB_TSD_REF_0_INTR_INTR 11
169 #define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 12
170 #define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 13
171 #define XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR 14
172 #define XPAR_DCR_INTC_0_PLB2OPB_BRIDGE_0_BUS_ERROR_DET_INTR 15
173 #define XPAR_DCR_INTC_0_PLB_V34_0_BUS_ERROR_DET_INTR 16
174 #define XPAR_DCR_INTC_0_OPB2PLB_BRIDGE_0_BUS_ERROR_DET_INTR 17
176 /******************************************************************/
178 #define XPAR_XTFT_NUM_INSTANCES 1
179 #define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200
180 #define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207
181 #define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0
183 /******************************************************************/
185 #define XPAR_XSYSACE_MEM_WIDTH 8
186 #define XPAR_XSYSACE_NUM_INSTANCES 1
187 #define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000
188 #define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF
189 #define XPAR_OPB_SYSACE_0_DEVICE_ID 0
190 #define XPAR_OPB_SYSACE_0_MEM_WIDTH 8
192 /******************************************************************/
194 #define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000
196 /******************************************************************/