2 * (C) Copyright 2007 Michal Simek
4 * Michal SIMEK <monstr@monstr.eu>
6 * SPDX-License-Identifier: GPL-2.0+
9 /* This is a board specific file. It's OK to include board specific
15 #include <asm/processor.h>
16 #include <asm/microblaze_intc.h>
20 #ifdef CONFIG_XILINX_GPIO
21 static int reset_pin = -1;
24 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
26 #ifdef CONFIG_XILINX_GPIO
28 gpio_direction_output(reset_pin, 1);
31 #ifdef CONFIG_XILINX_TB_WATCHDOG
32 hw_watchdog_disable();
35 puts ("Reseting board\n");
36 __asm__ __volatile__ (" mts rmsr, r0;" \
44 #ifdef CONFIG_XILINX_GPIO
45 reset_pin = gpio_alloc(CONFIG_SYS_GPIO_0_ADDR, "reset", 1);
47 gpio_request(reset_pin, "reset_pin");
57 int board_eth_init(bd_t *bis)
61 #ifdef CONFIG_XILINX_AXIEMAC
62 ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
63 XILINX_AXIDMA_BASEADDR);
66 #ifdef CONFIG_XILINX_EMACLITE
69 # ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
72 # ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
75 ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
79 #ifdef CONFIG_XILINX_LL_TEMAC
80 # ifdef XILINX_LLTEMAC_BASEADDR
81 # ifdef XILINX_LLTEMAC_FIFO_BASEADDR
82 ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
83 XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR);
84 # elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR
85 # if XILINX_LLTEMAC_SDMA_USE_DCR == 1
86 ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
87 XILINX_LL_TEMAC_M_SDMA_DCR,
88 XILINX_LLTEMAC_SDMA_CTRL_BASEADDR);
90 ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
91 XILINX_LL_TEMAC_M_SDMA_PLB,
92 XILINX_LLTEMAC_SDMA_CTRL_BASEADDR);
96 # ifdef XILINX_LLTEMAC_BASEADDR1
97 # ifdef XILINX_LLTEMAC_FIFO_BASEADDR1
98 ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
99 XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR1);
100 # elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1
101 # if XILINX_LLTEMAC_SDMA_USE_DCR == 1
102 ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
103 XILINX_LL_TEMAC_M_SDMA_DCR,
104 XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1);
106 ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
107 XILINX_LL_TEMAC_M_SDMA_PLB,
108 XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1);