1 /******************************************************************************
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30 * (c) Copyright 2002-2004 Xilinx Inc.
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38 ******************************************************************************/
39 /*****************************************************************************/
42 * @file xpacket_fifo_v1_00_b.h
44 * This component is a common component because it's primary purpose is to
45 * prevent code duplication in drivers. A driver which must handle a packet
46 * FIFO uses this component rather than directly manipulating a packet FIFO.
48 * A FIFO is a device which has dual port memory such that one user may be
49 * inserting data into the FIFO while another is consuming data from the FIFO.
50 * A packet FIFO is designed for use with packet protocols such as Ethernet and
51 * ATM. It is typically only used with devices when DMA and/or Scatter Gather
52 * is used. It differs from a nonpacket FIFO in that it does not provide any
53 * interrupts for thresholds of the FIFO such that it is less useful without
58 * This component has the capability to generate an interrupt when an error
59 * condition occurs. It is the user's responsibility to provide the interrupt
60 * processing to handle the interrupt. This component provides the ability to
61 * determine if that interrupt is active, a deadlock condition, and the ability
62 * to reset the FIFO to clear the condition. In this condition, the device which
63 * is using the FIFO should also be reset to prevent other problems. This error
64 * condition could occur as a normal part of operation if the size of the FIFO
65 * is not setup correctly. See the hardware IP specification for more details.
68 * MODIFICATION HISTORY:
70 * Ver Who Date Changes
71 * ----- ---- -------- -----------------------------------------------
72 * 1.00b rpm 03/26/02 First release
75 *****************************************************************************/
76 #ifndef XPACKET_FIFO_H /* prevent circular inclusions */
77 #define XPACKET_FIFO_H /* by using protection macros */
79 /***************************** Include Files *********************************/
81 #include "xbasic_types.h"
84 /************************** Constant Definitions *****************************/
87 * These constants specify the FIFO type and are mutually exclusive
89 #define XPF_READ_FIFO_TYPE 0 /* a read FIFO */
90 #define XPF_WRITE_FIFO_TYPE 1 /* a write FIFO */
93 * These constants define the offsets to each of the registers from the
94 * register base address, each of the constants are a number of bytes
96 #define XPF_RESET_REG_OFFSET 0UL
97 #define XPF_MODULE_INFO_REG_OFFSET 0UL
98 #define XPF_COUNT_STATUS_REG_OFFSET 4UL
101 * This constant is used with the Reset Register
103 #define XPF_RESET_FIFO_MASK 0x0000000A
106 * These constants are used with the Occupancy/Vacancy Count Register. This
107 * register also contains FIFO status
109 #define XPF_COUNT_MASK 0x0000FFFF
110 #define XPF_DEADLOCK_MASK 0x20000000
111 #define XPF_ALMOST_EMPTY_FULL_MASK 0x40000000
112 #define XPF_EMPTY_FULL_MASK 0x80000000
114 /**************************** Type Definitions *******************************/
117 * The XPacketFifo driver instance data. The driver is required to allocate a
118 * variable of this type for every packet FIFO in the device.
121 u32 RegBaseAddress; /* Base address of registers */
122 u32 IsReady; /* Device is initialized and ready */
123 u32 DataBaseAddress; /* Base address of data for FIFOs */
126 /***************** Macros (Inline Functions) Definitions *********************/
128 /*****************************************************************************/
131 * Reset the specified packet FIFO. Resetting a FIFO will cause any data
132 * contained in the FIFO to be lost.
134 * @param InstancePtr contains a pointer to the FIFO to operate on.
142 * Signature: void XPF_V100B_RESET(XPacketFifoV100b *InstancePtr)
144 ******************************************************************************/
145 #define XPF_V100B_RESET(InstancePtr) \
146 XIo_Out32((InstancePtr)->RegBaseAddress + XPF_RESET_REG_OFFSET, XPF_RESET_FIFO_MASK);
148 /*****************************************************************************/
151 * Get the occupancy count for a read packet FIFO and the vacancy count for a
152 * write packet FIFO. These counts indicate the number of 32-bit words
153 * contained (occupancy) in the FIFO or the number of 32-bit words available
154 * to write (vacancy) in the FIFO.
156 * @param InstancePtr contains a pointer to the FIFO to operate on.
160 * The occupancy or vacancy count for the specified packet FIFO.
164 * Signature: u32 XPF_V100B_GET_COUNT(XPacketFifoV100b *InstancePtr)
166 ******************************************************************************/
167 #define XPF_V100B_GET_COUNT(InstancePtr) \
168 (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
171 /*****************************************************************************/
174 * Determine if the specified packet FIFO is almost empty. Almost empty is
175 * defined for a read FIFO when there is only one data word in the FIFO.
177 * @param InstancePtr contains a pointer to the FIFO to operate on.
181 * TRUE if the packet FIFO is almost empty, FALSE otherwise.
185 * Signature: u32 XPF_V100B_IS_ALMOST_EMPTY(XPacketFifoV100b *InstancePtr)
187 ******************************************************************************/
188 #define XPF_V100B_IS_ALMOST_EMPTY(InstancePtr) \
189 (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
190 XPF_ALMOST_EMPTY_FULL_MASK)
192 /*****************************************************************************/
195 * Determine if the specified packet FIFO is almost full. Almost full is
196 * defined for a write FIFO when there is only one available data word in the
199 * @param InstancePtr contains a pointer to the FIFO to operate on.
203 * TRUE if the packet FIFO is almost full, FALSE otherwise.
207 * Signature: u32 XPF_V100B_IS_ALMOST_FULL(XPacketFifoV100b *InstancePtr)
209 ******************************************************************************/
210 #define XPF_V100B_IS_ALMOST_FULL(InstancePtr) \
211 (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
212 XPF_ALMOST_EMPTY_FULL_MASK)
214 /*****************************************************************************/
217 * Determine if the specified packet FIFO is empty. This applies only to a
220 * @param InstancePtr contains a pointer to the FIFO to operate on.
224 * TRUE if the packet FIFO is empty, FALSE otherwise.
228 * Signature: u32 XPF_V100B_IS_EMPTY(XPacketFifoV100b *InstancePtr)
230 ******************************************************************************/
231 #define XPF_V100B_IS_EMPTY(InstancePtr) \
232 (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
235 /*****************************************************************************/
238 * Determine if the specified packet FIFO is full. This applies only to a
241 * @param InstancePtr contains a pointer to the FIFO to operate on.
245 * TRUE if the packet FIFO is full, FALSE otherwise.
249 * Signature: u32 XPF_V100B_IS_FULL(XPacketFifoV100b *InstancePtr)
251 ******************************************************************************/
252 #define XPF_V100B_IS_FULL(InstancePtr) \
253 (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
256 /*****************************************************************************/
259 * Determine if the specified packet FIFO is deadlocked. This condition occurs
260 * when the FIFO is full and empty at the same time and is caused by a packet
261 * being written to the FIFO which exceeds the total data capacity of the FIFO.
262 * It occurs because of the mark/restore features of the packet FIFO which allow
263 * retransmission of a packet. The software should reset the FIFO and any devices
264 * using the FIFO when this condition occurs.
266 * @param InstancePtr contains a pointer to the FIFO to operate on.
270 * TRUE if the packet FIFO is deadlocked, FALSE otherwise.
274 * This component has the capability to generate an interrupt when an error
275 * condition occurs. It is the user's responsibility to provide the interrupt
276 * processing to handle the interrupt. This function provides the ability to
277 * determine if a deadlock condition, and the ability to reset the FIFO to
278 * clear the condition.
280 * In this condition, the device which is using the FIFO should also be reset
281 * to prevent other problems. This error condition could occur as a normal part
282 * of operation if the size of the FIFO is not setup correctly.
284 * Signature: u32 XPF_V100B_IS_DEADLOCKED(XPacketFifoV100b *InstancePtr)
286 ******************************************************************************/
287 #define XPF_V100B_IS_DEADLOCKED(InstancePtr) \
288 (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
291 /************************** Function Prototypes ******************************/
293 /* Standard functions */
295 XStatus XPacketFifoV100b_Initialize(XPacketFifoV100b * InstancePtr,
296 u32 RegBaseAddress, u32 DataBaseAddress);
297 XStatus XPacketFifoV100b_SelfTest(XPacketFifoV100b * InstancePtr, u32 FifoType);
301 XStatus XPacketFifoV100b_Read(XPacketFifoV100b * InstancePtr,
302 u8 * ReadBufferPtr, u32 ByteCount);
303 XStatus XPacketFifoV100b_Write(XPacketFifoV100b * InstancePtr,
304 u8 * WriteBufferPtr, u32 ByteCount);
306 #endif /* end of protection macro */