2 * Copyright 2008 Extreme Engineering Solutions, Inc.
3 * Copyright 2008 Freescale Semiconductor, Inc.
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * SPDX-License-Identifier: GPL-2.0+
14 struct fsl_e_tlb_entry tlb_table[] = {
15 /* TLB 0 - for temp stack in cache */
16 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
17 MAS3_SX|MAS3_SW|MAS3_SR, 0,
18 0, 0, BOOKE_PAGESZ_4K, 0),
19 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
20 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
21 MAS3_SX|MAS3_SW|MAS3_SR, 0,
22 0, 0, BOOKE_PAGESZ_4K, 0),
23 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
24 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
25 MAS3_SX|MAS3_SW|MAS3_SR, 0,
26 0, 0, BOOKE_PAGESZ_4K, 0),
27 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
28 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
29 MAS3_SX|MAS3_SW|MAS3_SR, 0,
30 0, 0, BOOKE_PAGESZ_4K, 0),
32 /* W**G* - NOR flashes */
33 /* This will be changed to *I*G* after relocation to RAM. */
34 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
35 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
36 0, 0, BOOKE_PAGESZ_256M, 1),
38 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
39 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
40 0, 1, BOOKE_PAGESZ_1M, 1),
42 /* *I*G* - NAND flash */
43 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
44 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
45 0, 2, BOOKE_PAGESZ_1M, 1),
49 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
50 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
51 0, 3, BOOKE_PAGESZ_1G, 1),
56 SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
57 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
58 0, 4, BOOKE_PAGESZ_256M, 1),
61 #if defined(CONFIG_PCI1) || defined(CONFIG_PCI2)
63 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS,
64 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
65 0, 5, BOOKE_PAGESZ_16M, 1),
69 int num_tlb_entries = ARRAY_SIZE(tlb_table);