1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008 Extreme Engineering Solutions, Inc.
10 * Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config
12 unsigned long get_board_sys_clk(ulong dummy)
14 #if defined(CONFIG_MPC85xx)
15 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
16 #elif defined(CONFIG_MPC86xx)
17 immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
18 volatile ccsr_gur_t *gur = &immap->im_gur;
21 if (in_be32(&gur->gpporcr) & 0x10000)
24 #ifdef CONFIG_ARCH_P2020
33 * Return DDR input clock - synchronous with SYSCLK or 66 MHz
34 * Note: 86xx doesn't support asynchronous DDR clk
36 unsigned long get_board_ddr_clk(ulong dummy)
38 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
39 u32 ddr_ratio = (in_be32(&gur->porpllsr) & 0x00003e00) >> 9;
42 return get_board_sys_clk(dummy);
44 #ifdef CONFIG_ARCH_P2020
45 if (in_be32(&gur->gpporcr) & 0x20000)