2 * Copyright 2008 Extreme Engineering Solutions, Inc.
4 * This driver support NAND devices which have address lines
5 * connected as ALE and CLE inputs.
7 * SPDX-License-Identifier: GPL-2.0+
15 * Hardware specific access to control-lines
17 static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
19 struct nand_chip *this = mtd->priv;
22 if (ctrl & NAND_CTRL_CHANGE) {
23 IO_ADDR_W = (ulong)this->IO_ADDR_W;
25 IO_ADDR_W &= ~(CONFIG_SYS_NAND_ACTL_CLE |
26 CONFIG_SYS_NAND_ACTL_ALE |
27 CONFIG_SYS_NAND_ACTL_NCE);
29 IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_CLE;
31 IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_ALE;
33 IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_NCE;
35 this->IO_ADDR_W = (void *)IO_ADDR_W;
38 if (cmd != NAND_CMD_NONE)
39 writeb(cmd, this->IO_ADDR_W);
42 int board_nand_init(struct nand_chip *nand)
44 nand->ecc.mode = NAND_ECC_SOFT;
45 nand->cmd_ctrl = nand_addr_hwcontrol;
46 nand->chip_delay = CONFIG_SYS_NAND_ACTL_DELAY;