2 * Copyright (C) 2016 NXP Semiconductors
3 * Author: Fabio Estevam <fabio.estevam@nxp.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/clock.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/mx7-pins.h>
11 #include <asm/arch/sys_proto.h>
13 #include <asm/mach-imx/hab.h>
14 #include <asm/mach-imx/iomux-v3.h>
15 #include <asm/mach-imx/mxc_i2c.h>
18 #include <fsl_esdhc.h>
21 #include <asm/arch/crm_regs.h>
24 #include <power/pmic.h>
25 #include <power/pfuze3000_pmic.h>
26 #include "../freescale/common/pfuze.h"
27 #include <asm/setup.h>
28 #include <asm/bootm.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
34 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
35 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
37 #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
38 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
40 #ifdef CONFIG_SYS_I2C_MXC
41 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
43 static struct i2c_pads_info i2c_pad_info1 = {
45 .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
46 .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
47 .gp = IMX_GPIO_NR(4, 8),
50 .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
51 .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
52 .gp = IMX_GPIO_NR(4, 9),
59 gd->ram_size = PHYS_SDRAM_SIZE;
61 /* Subtract the defined OPTEE runtime firmware length */
62 #ifdef CONFIG_OPTEE_TZDRAM_SIZE
63 gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE;
69 static iomux_v3_cfg_t const wdog_pads[] = {
70 MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
73 static iomux_v3_cfg_t const uart1_pads[] = {
74 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
75 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
78 static iomux_v3_cfg_t const usdhc3_pads[] = {
79 MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
80 MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
81 MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
82 MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
83 MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
84 MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
85 MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
86 MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
87 MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
88 MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
89 MX7D_PAD_SD3_RESET_B__SD3_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92 static void setup_iomux_uart(void)
94 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
97 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
101 int board_mmc_getcd(struct mmc *mmc)
103 /* Assume uSDHC3 emmc is always present */
107 int board_mmc_init(bd_t *bis)
109 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
110 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
112 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
115 int board_early_init_f(void)
124 static struct pmic *pfuze;
125 int power_init_board(void)
128 unsigned int reg, rev_id;
130 ret = power_pfuze3000_init(I2C_PMIC);
134 pfuze = pmic_get("PFUZE3000");
135 ret = pmic_probe(pfuze);
139 pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®);
140 pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
141 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
143 /* disable Low Power Mode during standby mode */
144 pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1);
150 int board_eth_init(bd_t *bis)
154 #ifdef CONFIG_USB_ETHER
155 ret = usb_eth_initialize(bis);
157 printf("Error %d registering USB ether.\n", ret);
165 /* address of boot parameters */
166 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
168 #ifdef CONFIG_SYS_I2C_MXC
169 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
179 if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
184 #ifdef CONFIG_OPTEE_TZDRAM_SIZE
185 unsigned long optee_start, optee_end;
187 optee_end = PHYS_SDRAM + PHYS_SDRAM_SIZE;
188 optee_start = optee_end - CONFIG_OPTEE_TZDRAM_SIZE;
190 printf("Board: WARP7 in %s mode OPTEE DRAM 0x%08lx-0x%08lx\n",
191 mode, optee_start, optee_end);
193 printf("Board: WARP7 in %s mode\n", mode);
199 int board_usb_phy_mode(int port)
201 return USB_INIT_DEVICE;
204 int board_late_init(void)
206 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
207 #ifdef CONFIG_SERIAL_TAG
208 struct tag_serialnr serialnr;
209 char serial_string[0x20];
212 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
214 set_wdog_reset(wdog);
217 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
218 * since we use PMIC_PWRON to reset the board.
220 clrsetbits_le16(&wdog->wcr, 0, 0x10);
222 #ifdef CONFIG_SECURE_BOOT
223 /* Determine HAB state */
224 env_set_ulong(HAB_ENABLED_ENVNAME, imx_hab_is_enabled());
226 env_set_ulong(HAB_ENABLED_ENVNAME, 0);
229 #ifdef CONFIG_SERIAL_TAG
230 /* Set serial# standard environment variable based on OTP settings */
231 get_board_serial(&serialnr);
232 snprintf(serial_string, sizeof(serial_string), "WaRP7-0x%08x%08x",
233 serialnr.low, serialnr.high);
234 env_set("serial#", serial_string);