1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 NXP Semiconductors
4 * Author: Fabio Estevam <fabio.estevam@nxp.com>
8 #include <asm/arch/clock.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/mx7-pins.h>
11 #include <asm/arch/sys_proto.h>
13 #include <asm/mach-imx/hab.h>
14 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/arch/crm_regs.h>
20 #include <power/pmic.h>
21 #include <power/pfuze3000_pmic.h>
22 #include "../freescale/common/pfuze.h"
23 #include <asm/setup.h>
24 #include <asm/bootm.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
33 gd->ram_size = PHYS_SDRAM_SIZE;
35 /* Subtract the defined OPTEE runtime firmware length */
36 #ifdef CONFIG_OPTEE_TZDRAM_SIZE
37 gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE;
43 static iomux_v3_cfg_t const wdog_pads[] = {
44 MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
47 static iomux_v3_cfg_t const uart1_pads[] = {
48 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
49 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
52 static void setup_iomux_uart(void)
54 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
57 int board_early_init_f(void)
65 int power_init_board(void)
68 int ret, dev_id, rev_id;
70 ret = pmic_get("pfuze3000@8", &dev);
76 dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
77 rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
78 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
80 /* disable Low Power Mode during standby mode */
81 pmic_reg_write(dev, PFUZE3000_LDOGCTL, 1);
87 int board_eth_init(bd_t *bis)
91 #ifdef CONFIG_USB_ETHER
92 ret = usb_eth_initialize(bis);
94 printf("Error %d registering USB ether.\n", ret);
102 /* address of boot parameters */
103 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
112 if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
117 #ifdef CONFIG_OPTEE_TZDRAM_SIZE
118 unsigned long optee_start, optee_end;
120 optee_end = PHYS_SDRAM + PHYS_SDRAM_SIZE;
121 optee_start = optee_end - CONFIG_OPTEE_TZDRAM_SIZE;
123 printf("Board: WARP7 in %s mode OPTEE DRAM 0x%08lx-0x%08lx\n",
124 mode, optee_start, optee_end);
126 printf("Board: WARP7 in %s mode\n", mode);
132 int board_late_init(void)
134 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
135 #ifdef CONFIG_SERIAL_TAG
136 struct tag_serialnr serialnr;
137 char serial_string[0x20];
140 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
142 set_wdog_reset(wdog);
145 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
146 * since we use PMIC_PWRON to reset the board.
148 clrsetbits_le16(&wdog->wcr, 0, 0x10);
150 #ifdef CONFIG_IMX_HAB
151 /* Determine HAB state */
152 env_set_ulong(HAB_ENABLED_ENVNAME, imx_hab_is_enabled());
154 env_set_ulong(HAB_ENABLED_ENVNAME, 0);
157 #ifdef CONFIG_SERIAL_TAG
158 /* Set serial# standard environment variable based on OTP settings */
159 get_board_serial(&serialnr);
160 snprintf(serial_string, sizeof(serial_string), "WaRP7-0x%08x%08x",
161 serialnr.low, serialnr.high);
162 env_set("serial#", serial_string);