2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
12 #include <asm/arch/clock.h>
13 #include <asm/arch/crm_regs.h>
14 #include <asm/arch/iomux.h>
15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/mx6-pins.h>
17 #include <asm/arch/mxc_hdmi.h>
18 #include <asm/arch/sys_proto.h>
20 #include <asm/imx-common/iomux-v3.h>
21 #include <asm/imx-common/boot_mode.h>
23 #include <asm/sizes.h>
25 #include <fsl_esdhc.h>
26 #include <ipu_pixfmt.h>
32 DECLARE_GLOBAL_DATA_PTR;
34 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
35 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
36 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
38 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
39 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
40 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
42 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
43 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
45 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2)
46 #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9)
47 #define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
51 gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
56 static iomux_v3_cfg_t const uart1_pads[] = {
57 MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
58 MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
61 iomux_v3_cfg_t const usdhc1_pads[] = {
62 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
63 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
64 MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
65 MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
66 MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
67 MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
68 /* Carrier MicroSD Card Detect */
69 MX6_PAD_GPIO_2__GPIO_1_2 | MUX_PAD_CTRL(NO_PAD_CTRL),
72 static iomux_v3_cfg_t const usdhc3_pads[] = {
73 MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
74 MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
75 MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
76 MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
77 MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
78 MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
79 /* SOM MicroSD Card Detect */
80 MX6_PAD_EIM_DA9__GPIO_3_9 | MUX_PAD_CTRL(NO_PAD_CTRL),
83 static iomux_v3_cfg_t const enet_pads[] = {
84 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
85 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
86 MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
87 MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
88 MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
89 MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
90 MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
91 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
92 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
93 MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
94 MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
95 MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
96 MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
97 MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
98 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
99 /* AR8031 PHY Reset */
100 MX6_PAD_EIM_D29__GPIO_3_29 | MUX_PAD_CTRL(NO_PAD_CTRL),
103 static void setup_iomux_uart(void)
105 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
108 static void setup_iomux_enet(void)
110 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
112 /* Reset AR8031 PHY */
113 gpio_direction_output(ETH_PHY_RESET, 0);
115 gpio_set_value(ETH_PHY_RESET, 1);
118 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
123 int board_mmc_getcd(struct mmc *mmc)
125 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
128 switch (cfg->esdhc_base) {
129 case USDHC1_BASE_ADDR:
130 ret = !gpio_get_value(USDHC1_CD_GPIO);
132 case USDHC3_BASE_ADDR:
133 ret = !gpio_get_value(USDHC3_CD_GPIO);
140 int board_mmc_init(bd_t *bis)
146 * Following map is done:
147 * (U-boot device node) (Physical Port)
149 * mmc1 Carrier board MicroSD
151 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
154 imx_iomux_v3_setup_multiple_pads(
155 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
156 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
157 usdhc_cfg[0].max_bus_width = 4;
158 gpio_direction_input(USDHC3_CD_GPIO);
161 imx_iomux_v3_setup_multiple_pads(
162 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
163 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
164 usdhc_cfg[1].max_bus_width = 4;
165 gpio_direction_input(USDHC1_CD_GPIO);
168 printf("Warning: you configured more USDHC controllers"
169 "(%d) then supported by the board (%d)\n",
170 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
174 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
180 static int mx6_rgmii_rework(struct phy_device *phydev)
184 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
185 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
186 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
187 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
189 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
192 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
194 /* introduce tx clock delay */
195 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
196 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
198 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
203 int board_phy_config(struct phy_device *phydev)
205 mx6_rgmii_rework(phydev);
207 if (phydev->drv->config)
208 phydev->drv->config(phydev);
213 #if defined(CONFIG_VIDEO_IPUV3)
214 static void enable_hdmi(void)
216 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
218 reg = readb(&hdmi->phy_conf0);
219 reg |= HDMI_PHY_CONF0_PDZ_MASK;
220 writeb(reg, &hdmi->phy_conf0);
223 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
224 writeb(reg, &hdmi->phy_conf0);
226 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
227 writeb(reg, &hdmi->phy_conf0);
228 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
231 static struct fb_videomode const hdmi = {
244 .vmode = FB_VMODE_NONINTERLACED
247 int board_video_skip(void)
251 ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24);
254 printf("HDMI cannot be configured: %d\n", ret);
261 static void setup_display(void)
263 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
264 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
267 /* Turn on IPU clock */
268 reg = readl(&mxc_ccm->CCGR3);
269 reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
270 writel(reg, &mxc_ccm->CCGR3);
272 /* Turn on HDMI PHY clock */
273 reg = readl(&mxc_ccm->CCGR2);
274 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
275 | MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
276 writel(reg, &mxc_ccm->CCGR2);
278 /* clear HDMI PHY reset */
279 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
281 reg = readl(&mxc_ccm->chsccdr);
282 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
283 | MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
284 | MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
285 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
286 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
287 | (CHSCCDR_PODF_DIVIDE_BY_3
288 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
289 | (CHSCCDR_IPU_PRE_CLK_540M_PFD
290 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
291 writel(reg, &mxc_ccm->chsccdr);
293 #endif /* CONFIG_VIDEO_IPUV3 */
295 int board_eth_init(bd_t *bis)
301 ret = cpu_eth_init(bis);
303 printf("FEC MXC: %s:failed\n", __func__);
308 int board_early_init_f(void)
311 #if defined(CONFIG_VIDEO_IPUV3)
318 * Do not overwrite the console
319 * Use always serial for U-Boot console
321 int overwrite_console(void)
326 #ifdef CONFIG_CMD_BMODE
327 static const struct boot_mode board_boot_modes[] = {
328 /* 4 bit bus width */
329 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
330 {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
335 int board_late_init(void)
337 #ifdef CONFIG_CMD_BMODE
338 add_board_boot_modes(board_boot_modes);
346 /* address of boot parameters */
347 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
354 puts("Board: Wandboard\n");