board/wandboard/wandboard.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2014 O.S. Systems Software LTDA.
   5  *
   6  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   7  */
   8
   9 #include <init.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/arch/mxc_hdmi.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/gpio.h>
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <asm/mach-imx/mxc_i2c.h>
  20 #include <asm/mach-imx/boot_mode.h>
  21 #include <asm/mach-imx/video.h>
  22 #include <asm/mach-imx/sata.h>
  23 #include <asm/io.h>
  24 #include <env.h>
  25 #include <linux/sizes.h>
  26 #include <common.h>
  27 #include <miiphy.h>
  28 #include <netdev.h>
  29 #include <phy.h>
  30 #include <i2c.h>
  31 #include <power/pmic.h>
  32 #include <power/pfuze100_pmic.h>
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  37         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  38         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  39
  40 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  41         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  42
  43 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  44         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  45         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  46
  47 #define ETH_PHY_RESET           IMX_GPIO_NR(3, 29)
  48 #define ETH_PHY_AR8035_POWER    IMX_GPIO_NR(7, 13)
  49 #define REV_DETECTION           IMX_GPIO_NR(2, 28)
  50
  51 /* Speed defined in Kconfig is only applicable when not using DM_I2C.  */
  52 #ifdef CONFIG_DM_I2C
  53 #define I2C1_SPEED_NON_DM       0
  54 #define I2C2_SPEED_NON_DM       0
  55 #else
  56 #define I2C1_SPEED_NON_DM       CONFIG_SYS_MXC_I2C1_SPEED
  57 #define I2C2_SPEED_NON_DM       CONFIG_SYS_MXC_I2C2_SPEED
  58 #endif
  59
  60 static bool with_pmic;
  61
  62 int dram_init(void)
  63 {
  64         gd->ram_size = imx_ddr_size();
  65
  66         return 0;
  67 }
  68
  69 static iomux_v3_cfg_t const uart1_pads[] = {
  70         IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  71         IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  72 };
  73
  74 static iomux_v3_cfg_t const enet_pads[] = {
  75         /* AR8031 PHY Reset */
  76         IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  77 };
  78
  79 static iomux_v3_cfg_t const enet_ar8035_power_pads[] = {
  80         /* AR8035 POWER */
  81         IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  82 };
  83
  84 static iomux_v3_cfg_t const rev_detection_pad[] = {
  85         IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28  | MUX_PAD_CTRL(NO_PAD_CTRL)),
  86 };
  87
  88 static void setup_iomux_uart(void)
  89 {
  90         SETUP_IOMUX_PADS(uart1_pads);
  91 }
  92
  93 static void setup_iomux_enet(void)
  94 {
  95         SETUP_IOMUX_PADS(enet_pads);
  96
  97         if (with_pmic) {
  98                 SETUP_IOMUX_PADS(enet_ar8035_power_pads);
  99                 /* enable AR8035 POWER */
 100                 gpio_request(ETH_PHY_AR8035_POWER, "PHY_POWER");
 101                 gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
 102         }
 103         /* wait until 3.3V of PHY and clock become stable */
 104         mdelay(10);
 105
 106         /* Reset AR8031 PHY */
 107         gpio_request(ETH_PHY_RESET, "PHY_RESET");
 108         gpio_direction_output(ETH_PHY_RESET, 0);
 109         mdelay(10);
 110         gpio_set_value(ETH_PHY_RESET, 1);
 111         udelay(100);
 112 }
 113
 114 static int ar8031_phy_fixup(struct phy_device *phydev)
 115 {
 116         unsigned short val;
 117         int mask;
 118
 119         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 120         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 121         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 122         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 123
 124         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 125         if (with_pmic)
 126                 mask = 0xffe7;  /* AR8035 */
 127         else
 128                 mask = 0xffe3;  /* AR8031 */
 129
 130         val &= mask;
 131         val |= 0x18;
 132         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 133
 134         /* introduce tx clock delay */
 135         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 136         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 137         val |= 0x0100;
 138         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 139
 140         return 0;
 141 }
 142
 143 int board_phy_config(struct phy_device *phydev)
 144 {
 145         ar8031_phy_fixup(phydev);
 146
 147         if (phydev->drv->config)
 148                 phydev->drv->config(phydev);
 149
 150         return 0;
 151 }
 152
 153 #if defined(CONFIG_VIDEO_IPUV3)
 154 struct i2c_pads_info mx6q_i2c2_pad_info = {
 155         .scl = {
 156                 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
 157                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 158                 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
 159                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 160                 .gp = IMX_GPIO_NR(4, 12)
 161         },
 162         .sda = {
 163                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
 164                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 165                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
 166                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 167                 .gp = IMX_GPIO_NR(4, 13)
 168         }
 169 };
 170
 171 struct i2c_pads_info mx6dl_i2c2_pad_info = {
 172         .scl = {
 173                 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
 174                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 175                 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
 176                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 177                 .gp = IMX_GPIO_NR(4, 12)
 178         },
 179         .sda = {
 180                 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
 181                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 182                 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
 183                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 184                 .gp = IMX_GPIO_NR(4, 13)
 185         }
 186 };
 187
 188 struct i2c_pads_info mx6q_i2c3_pad_info = {
 189         .scl = {
 190                 .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL
 191                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 192                 .gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05
 193                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 194                 .gp = IMX_GPIO_NR(1, 5)
 195         },
 196         .sda = {
 197                 .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA
 198                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 199                 .gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11
 200                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 201                 .gp = IMX_GPIO_NR(7, 11)
 202         }
 203 };
 204
 205 struct i2c_pads_info mx6dl_i2c3_pad_info = {
 206         .scl = {
 207                 .i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL
 208                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 209                 .gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05
 210                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 211                 .gp = IMX_GPIO_NR(1, 5)
 212         },
 213         .sda = {
 214                 .i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA
 215                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 216                 .gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11
 217                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 218                 .gp = IMX_GPIO_NR(7, 11)
 219         }
 220 };
 221
 222 static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
 223         IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
 224         IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
 225         IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
 226         IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
 227         IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
 228         IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
 229         IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
 230         IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
 231         IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
 232         IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
 233         IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
 234         IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
 235         IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
 236         IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
 237         IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
 238         IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
 239         IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
 240         IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
 241         IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
 242         IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
 243         IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
 244         IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
 245         IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
 246         IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
 247         IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
 248 };
 249
 250 static void do_enable_hdmi(struct display_info_t const *dev)
 251 {
 252         imx_enable_hdmi_phy();
 253 }
 254
 255 static int detect_i2c(struct display_info_t const *dev)
 256 {
 257 #ifdef CONFIG_DM_I2C
 258         struct udevice *bus, *udev;
 259         int rc;
 260
 261         rc = uclass_get_device_by_seq(UCLASS_I2C, dev->bus, &bus);
 262         if (rc)
 263                 return rc;
 264         rc = dm_i2c_probe(bus, dev->addr, 0, &udev);
 265         if (rc)
 266                 return 0;
 267         return 1;
 268 #else
 269         return (0 == i2c_set_bus_num(dev->bus)) &&
 270                         (0 == i2c_probe(dev->addr));
 271 #endif
 272 }
 273
 274 static void enable_fwadapt_7wvga(struct display_info_t const *dev)
 275 {
 276         SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
 277
 278         gpio_request(IMX_GPIO_NR(2, 10), "DISP0_BKLEN");
 279         gpio_request(IMX_GPIO_NR(2, 11), "DISP0_VDDEN");
 280         gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
 281         gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
 282 }
 283
 284 struct display_info_t const displays[] = {{
 285         .bus    = -1,
 286         .addr   = 0,
 287         .pixfmt = IPU_PIX_FMT_RGB24,
 288         .detect = detect_hdmi,
 289         .enable = do_enable_hdmi,
 290         .mode   = {
 291                 .name           = "HDMI",
 292                 .refresh        = 60,
 293                 .xres           = 1024,
 294                 .yres           = 768,
 295                 .pixclock       = 15385,
 296                 .left_margin    = 220,
 297                 .right_margin   = 40,
 298                 .upper_margin   = 21,
 299                 .lower_margin   = 7,
 300                 .hsync_len      = 60,
 301                 .vsync_len      = 10,
 302                 .sync           = FB_SYNC_EXT,
 303                 .vmode          = FB_VMODE_NONINTERLACED
 304 } }, {
 305         .bus    = 1,
 306         .addr   = 0x10,
 307         .pixfmt = IPU_PIX_FMT_RGB666,
 308         .detect = detect_i2c,
 309         .enable = enable_fwadapt_7wvga,
 310         .mode   = {
 311                 .name           = "FWBADAPT-LCD-F07A-0102",
 312                 .refresh        = 60,
 313                 .xres           = 800,
 314                 .yres           = 480,
 315                 .pixclock       = 33260,
 316                 .left_margin    = 128,
 317                 .right_margin   = 128,
 318                 .upper_margin   = 22,
 319                 .lower_margin   = 22,
 320                 .hsync_len      = 1,
 321                 .vsync_len      = 1,
 322                 .sync           = 0,
 323                 .vmode          = FB_VMODE_NONINTERLACED
 324 } } };
 325 size_t display_count = ARRAY_SIZE(displays);
 326
 327 static void setup_display(void)
 328 {
 329         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 330         int reg;
 331
 332         enable_ipu_clock();
 333         imx_setup_hdmi();
 334
 335         reg = readl(&mxc_ccm->chsccdr);
 336         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 337                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 338         writel(reg, &mxc_ccm->chsccdr);
 339
 340         /* Disable LCD backlight */
 341         SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
 342         gpio_request(IMX_GPIO_NR(4, 20), "LCD_BKLEN");
 343         gpio_direction_input(IMX_GPIO_NR(4, 20));
 344 }
 345 #endif /* CONFIG_VIDEO_IPUV3 */
 346
 347 int board_early_init_f(void)
 348 {
 349         setup_iomux_uart();
 350 #ifdef CONFIG_SATA
 351         setup_sata();
 352 #endif
 353
 354         return 0;
 355 }
 356
 357 #define PMIC_I2C_BUS            2
 358
 359 int power_init_board(void)
 360 {
 361         struct udevice *dev;
 362         int reg, ret;
 363
 364         ret = pmic_get("pfuze100@8", &dev);
 365         if (ret < 0) {
 366                 debug("pmic_get() ret %d\n", ret);
 367                 return 0;
 368         }
 369
 370         reg = pmic_reg_read(dev, PFUZE100_DEVICEID);
 371         if (reg < 0) {
 372                 debug("pmic_reg_read() ret %d\n", reg);
 373                 return 0;
 374         }
 375         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 376         with_pmic = true;
 377
 378         /* Set VGEN2 to 1.5V and enable */
 379         reg = pmic_reg_read(dev, PFUZE100_VGEN2VOL);
 380         reg &= ~(LDO_VOL_MASK);
 381         reg |= (LDOA_1_50V | (1 << (LDO_EN)));
 382         pmic_reg_write(dev, PFUZE100_VGEN2VOL, reg);
 383         return 0;
 384 }
 385
 386 /*
 387  * Do not overwrite the console
 388  * Use always serial for U-Boot console
 389  */
 390 int overwrite_console(void)
 391 {
 392         return 1;
 393 }
 394
 395 #ifdef CONFIG_CMD_BMODE
 396 static const struct boot_mode board_boot_modes[] = {
 397         /* 4 bit bus width */
 398         {"mmc0",          MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 399         {"mmc1",          MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 400         {NULL,   0},
 401 };
 402 #endif
 403
 404 static bool is_revc1(void)
 405 {
 406         SETUP_IOMUX_PADS(rev_detection_pad);
 407         gpio_request(REV_DETECTION, "REV_DETECT");
 408         gpio_direction_input(REV_DETECTION);
 409
 410         if (gpio_get_value(REV_DETECTION))
 411                 return true;
 412         else
 413                 return false;
 414 }
 415
 416 static bool is_revd1(void)
 417 {
 418         if (with_pmic)
 419                 return true;
 420         else
 421                 return false;
 422 }
 423
 424 int board_late_init(void)
 425 {
 426 #ifdef CONFIG_CMD_BMODE
 427         add_board_boot_modes(board_boot_modes);
 428 #endif
 429
 430 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 431         if (is_mx6dqp())
 432                 env_set("board_rev", "MX6QP");
 433         else if (is_mx6dq())
 434                 env_set("board_rev", "MX6Q");
 435         else
 436                 env_set("board_rev", "MX6DL");
 437
 438         if (is_revd1())
 439                 env_set("board_name", "D1");
 440         else if (is_revc1())
 441                 env_set("board_name", "C1");
 442         else
 443                 env_set("board_name", "B1");
 444 #endif
 445         setup_iomux_enet();
 446
 447         if (is_revd1())
 448                 puts("Board: Wandboard rev D1\n");
 449         else if (is_revc1())
 450                 puts("Board: Wandboard rev C1\n");
 451         else
 452                 puts("Board: Wandboard rev B1\n");
 453
 454         return 0;
 455 }
 456
 457 int board_init(void)
 458 {
 459         /* address of boot parameters */
 460         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 461
 462 #if defined(CONFIG_VIDEO_IPUV3)
 463         setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
 464         if (is_mx6dq() || is_mx6dqp()) {
 465                 setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6q_i2c2_pad_info);
 466                 setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6q_i2c3_pad_info);
 467         } else {
 468                 setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
 469                 setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6dl_i2c3_pad_info);
 470         }
 471
 472         setup_display();
 473 #endif
 474
 475         return 0;
 476 }
 477
 478 #ifdef CONFIG_SPL_LOAD_FIT
 479 int board_fit_config_name_match(const char *name)
 480 {
 481         if (is_mx6dq()) {
 482                 if (!strcmp(name, "imx6q-wandboard-revd1"))
 483                         return 0;
 484         } else if (is_mx6dqp()) {
 485                 if (!strcmp(name, "imx6qp-wandboard-revd1"))
 486                         return 0;
 487         } else if (is_mx6dl() || is_mx6solo()) {
 488                 if (!strcmp(name, "imx6dl-wandboard-revd1"))
 489                         return 0;
 490         }
 491
 492         return -EINVAL;
 493 }
 494 #endif